M95320-WMN6P STMicroelectronics, M95320-WMN6P Datasheet - Page 20

• Manufacturer Part Number: M95320-WMN6P
• Description: IC EEPROM 32KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95320-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 32K (4K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 4096 X 8
• Interface Type: Serial, SPI
• Clock Frequency: 10MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8611-5; M95320-WMN6P

Instructions
Table 5.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in
20/44
signal
W
1
0
1
0
SRWD
bit
0
0
1
1
Protection modes
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
●
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered:
●
●
The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write
Protect (W) high.
If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can
never be activated, and only the Software-protected mode (SPM), using the Block protect
(BP1, BP0) bits in the Status Register, can be used.
Table 6.
1. b15 to b12 are Don’t Care.
Hardware
protected
protected
Software
(SPM)
(HPM)
Mode
If Write Protect (W) is driven high, it is possible to write to the Status Register provided
that the Write enable latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the Write Enable latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register,
are also hardware-protected against data modification.
by setting the Status register write disable (SRWD) bit after driving Write Protect (W)
low
or by driving Write Protect (W) low after setting the Status register write disable
(SRWD) bit.
Address bits
Device
Address range bits
Status Register is Writable (if the WREN
instruction has set the WEL bit)
The values in the BP1 and BP0 bits can be
changed
Status Register is Hardware write protected
The values in the BP1 and BP0 bits cannot
be changed
Write protection of the Status Register
Doc ID 5711 Rev 12
(1)
32 Kbit devices
A11-A0
Write Protected
Write Protected
Protected area
Table
M95320, M95320-W, M95320-R
5.
Memory content
Table
(1)
Unprotected area
Ready to accept
Write instructions
Ready to accept
Write instructions
2.
(1)