M45PE80-VMP6 NUMONYX, M45PE80-VMP6 Datasheet - Page 18

• Manufacturer Part Number: M45PE80-VMP6
• Description: IC FLASH 8MBIT 25MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMP6

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 25MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M45PE80
Page Write (PW)
The Page Write (PW) instruction allows bytes to
be written in the memory. Before it can be accept-
ed, a Write Enable (WREN) instruction must previ-
ously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable Latch (WEL).
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). The rest of
the page remains unchanged if no power failure
occurs during this write cycle.
The Page Write (PW) instruction performs a page
erase cycle even if only one byte is updated.
If the 8 least significant address bits (A7-A0) are
not all zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are written
from the start address of the same page (the one
whose 8 least significant address bits (A7-A0) are
all zero). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
Figure 14. Page Write (PW) Instruction Sequence
Note: 1. Address bits A23 to A20 are Don’t Care
18/36
2. 1
S
C
D
S
C
D
n
256
MSB
7
40
0
6
41
1
5
42
Data Byte 2
2
Instruction
4
43 44 45 46 47 48 49 50
3
3
4
2
5
1
Figure
6
0
MSB
7
7
MSB
23
14..
8
6
22 21
9 10
5
Data Byte 3
24-Bit Address
4
51
data bytes are guaranteed to be written correctly
within the same page. If less than 256 Data bytes
are sent to device, they are correctly written at the
requested addresses without having any effects
on the other bytes of the same page.
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Write (PW) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Write cycle (whose duration is t
initiated. While the Page Write cycle is in progress,
the Status Register may be read to check the val-
ue of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Page
Write cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the
Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Write (PW) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
3
52 53 54 55
3
28 29 30 31 32 33 34 35
2
2
1
1
0
0
MSB
7
MSB
7
6
6
5
Data Byte 1
5
Data Byte n
4
4
3
36 37 38
3
2
2
1
1
0
39
0
AI04045
PW
) is