M29F400BB70N6 NUMONYX, M29F400BB70N6 Datasheet - Page 13
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M29F400BB70N6
Manufacturer Part Number
M29F400BB70N6
Description
IC FLASH 4MBIT 70NS 48TSOP
Manufacturer
NUMONYX
Datasheet
1.M29F400BB70N6T.pdf
(40 pages)
Specifications of M29F400BB70N6
Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
4M (512K x 8 or 256K x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M29F400BB70N6
Manufacturer:
STM
Quantity:
274
Company:
Part Number:
M29F400BB70N6
Manufacturer:
NEC
Quantity:
71
M29F400BT, M29F400BB
3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See
Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
AC Waveforms, and
becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See
and
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
impedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at V
Current, I
I
11., DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
CC3
, Chip Enable should be held within V
Table 13.
CC2
. To further reduce the Supply Current to the CMOS Standby Supply Current,
and
IH
. The Data Inputs/Outputs will output the value, see
CC4
Table
Table
, for Program or Erase operations until the operation completes.
14., Write AC Characteristics, for details of the timing requirements.
IH
12., Read AC Characteristics, for details of when the output
the Supply Current is reduced to the TTL Standby Supply
IH
, the Data Inputs/Outputs pins are placed in the high-
IL
, to Chip Enable and Output Enable and keeping Write
CC
Figure 9.
± 0.2V. For Standby current levels see
and
Figure
Table 2.
10., Write AC Waveforms,
Figure
and
Table
Bus operations
8., Read Mode
3., Bus
Table
13/40
IH
IH
,
.