CY7C056V-12AXC Cypress Semiconductor Corp, CY7C056V-12AXC Datasheet - Page 9

IC SRAM 576KBIT 12NS 144LQFP

CY7C056V-12AXC

Manufacturer Part Number
CY7C056V-12AXC
Description
IC SRAM 576KBIT 12NS 144LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of CY7C056V-12AXC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
576K (16K x 36)
Speed
12ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Density
576Kb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
14b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
385mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Word Size
36b
Number Of Words
16K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C056V-12AXC
Manufacturer:
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Quantity:
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Part Number:
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6 393
Part Number:
CY7C056V-12AXC
Manufacturer:
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Quantity:
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Document #: 38-06055 Rev. *B
Switching Characteristics
Data Retention Mode
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
Notes:
21. t
22. CE = V
t
t
t
t
t
t
t
t
t
t
t
1. Chip Enable (CE)
2. CE must be kept between V
3. The RAM can begin operation >t
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
Busy Timing
Interrupt Timing
Semaphore Timing
retention, within V
during the power-up and power-down transitions.
minimum operating voltage (3.15 volts).
Parameter
BDD
[21]
is a calculated parameter and is the greater of t
DD
, V
in
= V
[20]
SS
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W LOW after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
[20]
to V
[3]
DD
DD
must be held HIGH during data
to V
, T
A
= 25°C. This parameter is guaranteed but not tested.
DD
DD
– 0.2V.
Description
– 0.2V and 70% of V
Over the Operating Range
RC
after V
WDD
DD
–t
PWE
reaches the
(actual) or t
DD
DDD
[14]
Min.
11
10
5
0
5
5
–t
(continued)
SD
Timing
V
CE
ICC
-12
CC
(actual).
Parameter
Max.
DR1
12
12
12
12
12
Min.
13
10
CY7C056V
CY7C057V
5
0
5
5
3.15V
-15
@ VDD
Data Retention Mode
Test Conditions
V
CC
Max.
15
15
15
15
15
V
to V
CC
DR
> 2.0V
CC
= 2V
– 0.2V
Min.
15
10
5
0
5
5
3.15V
-20
[22]
Max.
CY7C056V
CY7C057V
20
20
20
20
20
Max.
50
Page 9 of 23
V
t
IH
RC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
µA
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