CY7C056V-12AXC Cypress Semiconductor Corp, CY7C056V-12AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C056V-12AXC
• Description: IC SRAM 576KBIT 12NS 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C056V-12AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 576K (16K x 36)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-06055 Rev. *B
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
15. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
16. At any given temperature and voltage condition for any given device, t
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
20. Test conditions used are Load 1.
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
LZBE
HZBE
PU
PD
ABE
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
Read Cycle
Write Cycle
Busy Timing
Parameter
[3, 18]
[3, 18]
[15]
I
refer to Read Timing with Busy waveform.
OI
[15]
[3, 15]
[3, 15]
[19]
[19]
/I
[3, 14, 17, 18]
[3, 16, 17, 18]
[3, 16, 17, 18]
[3, 16, 17, 18]
[17, 18]
[17, 18]
OH
and 10-pF load capacitance.
[20]
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
Byte Enable to Low Z
Byte Enable to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
Description
Over the Operating Range
HZCE
[14]
Min.
is less than t
12
12
10
10
10
10
3
0
3
3
0
0
0
0
3
-12
Max.
12
12
10
10
10
12
12
10
25
20
12
12
12
LZCE
8
and t
Min.
HZOE
15
15
12
12
12
10
CY7C056V
CY7C057V
3
0
3
3
0
0
0
0
3
is less than t
-15
Max.
15
15
10
10
10
10
15
15
10
30
25
15
15
15
LZOE
.
Min.
20
20
15
15
15
15
3
0
3
3
0
0
0
0
3
-20
SCE
Max.
time.
CY7C056V
CY7C057V
20
20
12
12
12
12
20
20
12
45
30
20
20
20
Page 8 of 23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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