CY7C024-25JXCT Cypress Semiconductor Corp, CY7C024-25JXCT Datasheet - Page 5

• Manufacturer Part Number: CY7C024-25JXCT
• Description: IC SRAM 64KBIT 25NS 84PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C024-25JXCT

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 64K (4K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-06035 Rev. *C
Busy
The CY7C024/0241 and CY7C025/0251 provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within t
determine which port has access. If t
will definitely gain permission to the location, but which one is
not predictable. BUSY will be asserted t
match or t
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (t
Otherwise, the slave chip may begin a write cycle during a
contention situation.When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C024/0241 and CY7C025/0251 provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports.The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch
by writing a zero to a semaphore location. The left port then
verifies its success in setting the latch by reading it. After
writing to the semaphore, SEM or OE must be deasserted for
tSOP before attempting to read the semaphore. The
semaphore value will be available t
Table 1. Non-Contending Read/Write
CE
H
H
H
X
L
L
L
L
L
L
X
X
X
L
L
BLC
R/W
H
H
H
H
H
X
X
L
L
L
X
X
X
after CE is taken LOW.
OE
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
PS
Inputs
of each other, the busy logic will
UB
X
H
H
H
X
X
H
X
H
X
L
L
L
L
L
SWRD
PS
LB
X
H
H
H
X
X
H
X
H
X
L
L
L
L
L
BLA
+ t
is violated, one port
DOE
after an address
SEM
after the rising
H
H
H
H
H
H
H
H
X
BLC
L
L
L
L
L
L
or t
High Z
High Z
High Z
Data In
Data In
High Z
Data Out
Data Out
High Z
Data Out
Data Out
Data In
Data In
BLA
I/O
).
0
–I/O
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the
left side will succeed in gaining control of the semaphore. If the
left side no longer requires the semaphore, a one is written to
cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to
access the semaphore within t
semaphore will definitely be obtained by one side or the other,
but there is no guarantee which side will control the
semaphore.
7
[2]
Outputs
High Z
High Z
Data In
High Z
Data In
Data Out
High Z
Data Out
High Z
Data Out
Data Out
Data In
Data In
I/O
8
–I/O
15
[3]
Deselected: Power-Down
Deselected: Power-Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write D
Write D
Not Allowed
Not Allowed
IN0
IN0
SPS
CY7C024/0241
CY7C025/0251
into Semaphore Flag
into Semaphore Flag
Operation
of each other, the
0
is used. If a zero is
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