M48Z35AV-10MH6F STMicroelectronics, M48Z35AV-10MH6F Datasheet - Page 10

• Manufacturer Part Number: M48Z35AV-10MH6F
• Description: IC NVSRAM 256KBIT 100NS 28SOIC
• Manufacturer: STMicroelectronics

Specifications of M48Z35AV-10MH6F

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4727-2

Operating modes
2.2
10/25
WRITE mode
The M48Z35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
Figure 6.
Figure 7.
A0-A14
E
W
DQ0-DQ7
A0-A14
E
W
DQ0-DQ7
WRITE enable controlled, WRITE mode AC waveforms
Chip enable controlled, WRITE mode AC waveforms
tAVEL
tAVWL
tAVEL
tAVWL
Doc ID 6784 Rev 8
tWLQZ
EHAX
WHDX
from chip enable or t
tAVEH
tAVWH
afterward. G should be kept high during WRITE
WLQZ
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
after W falls.
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
from WRITE enable prior
tEHDX
DVWH
tWHQX
tEHAX
tWHAX
prior to the
M48Z35AV
AI00927
AI00926