CY7C1355B-117AC Cypress Semiconductor Corp, CY7C1355B-117AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1355B-117AC
• Description: IC SRAM 9MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1355B-117AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1502

Document #: 38-05117 Rev. *C
CY7C1355B–Pin Definitions
DQ
DQP
MODE
V
V
V
TDO
TDI
TMS
DD
DDQ
SS
Name
s
[A:D]
52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
12,13,18,19,
22,23,24,25,
26,40,55,60,
15,41,65,91 J2,C4,J4,
54,61,70,77
67,71,76,90
2,3,6,7,8,9,
4,11,20,27,
5,10,17,21,
51,80,1,30 P6,D6,D2,
TQFP
28,29
31
-
-
-
F6,G6,H6,
D7,E7,G7,
H7,D1,E1,
G1,H1,E2,
F2,G2,H2,
K6,L6,M6,
N6,K7,L7,
N7,P7,E6,
K1,L1,N1,
D3,E3,F3,
P3,D5,E5,
F5,H5,K5,
M5,N5,P5
P1,K2,L2,
A1,F1,J1,
A7,F7,J7,
M1,U1,
M3,N3,
H3,K3,
M2,N2
M7,U7
R4,J6
BGA
P2
R3
U5
U3
U2
(continued)
J6,J7,K5,K6,
K7,L5,L6,L7,
N11,C11,C1,
M5,M6,M7,
G4,G8,H2,
G6,G7,H5,
G1,D2,E2,
D4,D8,E4,
C3,C9,D3,
L9,M3,M9,
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
D1,E1,F1,
K1,L1,M1,
D9,E3,E9,
F3,F9,G3,
F6,F7,G5,
F2,G2,J1,
E8,F4,F8,
H4,H8,J4,
L4,L8,M4,
K3,K9,L3,
E6,E7,F5,
H6,H7,J5,
J8,K4,K8,
G9,J3,J9,
L10,M10,
D10,E10,
F10,G10,
M11,L11,
D11,E11,
F11,G11,
J10,K10,
J2,K2,L2
K11,J11,
N3,N9
N4,N8
fBGA
M2,
N1
R1
M8
R5
P7
P5
Synchronous
Input Strap Pin Mode Input. Selects the burst order of the device.
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Synchronous
JTAG serial
JTAG serial
JTAG serial
I/O Power
Ground
Supply
output
input
input
I/O-
I/O-
I/O
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented
during the previous clock rise of the Read cycle. The di-
rection of the pins is controlled by OE. When OE is assert-
ed LOW, the pins behave as outputs. When HIGH, DQ
and DQP
outputs are automatically three-stated during the data
portion of a Write sequence, during the first clock when
emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O Lines. Functionally, these
signals are identical to DQ
DQP
When tied to Gnd selects linear burst sequence. When
tied to V
sequence.
Power supply for the I/O circuitry.
Ground for the device.
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK. If the JTAG feature is not being
utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be left floating or connected to V
up resistor. This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be disconnected or connected to V
not available on TQFP packages.
[A:D]
DD
[A:D]
is controlled by BW
or left floating selects interleaved burst
are placed in a three-state condition. The
Description
s
. During Write sequences,
[A:D]
correspondingly.
CY7C1355B
CY7C1357B
DD
DD
through a pull
Page 8 of 32
. This pin is
s