CY7C1355B-117AC Cypress Semiconductor Corp, CY7C1355B-117AC Datasheet - Page 10

• Manufacturer Part Number: CY7C1355B-117AC
• Description: IC SRAM 9MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1355B-117AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1502

Document #: 38-05117 Rev. *C
CY7C1357B–Pin Definitions
CEN
ZZ
DQ
DQP
MODE
V
V
V
TDO
DD
DDQ
SS
Name
s
[A:B]
58,59,62,63,
68,69,72,73,
26,40,55,60,
18,19,22,23
15,41,65,91 C4,J2,J4,
54,61,70,77
67,71,76,90
4,11,20,27,
5,10,17,21,
8,9,12,13,
TQFP
74,24
87
64
31
-
P7,K7,G7,
E2,G2,K2,
M1,M7,U1
D3,D5,E3,
E7,F6,H6,
L6,N6,D1,
H1,L1,N1,
H5,K3,K5,
A1,A7,F1,
E5,F3,F5,
N5,P3,P5
F7,J1,J7,
M5,N3,
G5,H3,
L3,M3,
D6,P2
J6,R4
BGA
,U7
M4
M2
R3
U5
T7
(continued)
J6,J7,K5,K6,
K7,L5,L6,L7,
F11,G11,J1,
M5,M6,M7,
G4,G8,H2,
L9,M3,M9,
G6,G7,H5,
D4,D8,E4,
C3,C9,D3,
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
K1,L1,M1,
D2,E2,F2,
H4,H8,J4,
L4,L8,M4,
D9,E3,E9,
F3,F9,G3,
E6,E7,F5,
F6,F7,G5,
H6,H7,J5,
E8,F4,F8,
J8,K4,K8,
K3,K9,L3,
G9,J3,J9,
L10,M10,
J10,K10,
D11,E11,
C11,N1
N3,N9
N4,N8
fBGA
H11
M8
A7
G2
R1
P7
Synchronous
Input Strap Pin Mode Input. Selects the burst order of the device.
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
JTAG serial
I/O Power
Ground
Supply
output
Input-
Input-
I/O-
I/O-
I/O
Clock Enable Input, active LOW. When asserted LOW
the Clock signal is recognized by the SRAM. When deas-
serted HIGH the Clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
ZZ “Sleep” Input, active HIGH. When asserted HIGH
places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge of
CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented
during the previous clock rise of the Read cycle. The di-
rection of the pins is controlled by OE. When OE is assert-
ed LOW, the pins behave as outputs. When HIGH, DQ
and DQP
outputs are automatically three-stated during the data por-
tion of a Write sequence, during the first clock when
emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
Bidirectional Data Parity I/O Lines. Functionally, these
signals are identical to DQ
DQP
When tied to Gnd selects linear burst sequence. When
tied to V
sequence.
Power supply for the I/O circuitry.
Ground for the device.
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK. If the JTAG feature is not being
utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
[A:B]
DD
[A:B]
is controlled by BW
or left floating selects interleaved burst
are placed in a three-state condition. The
Description
s
. During Write sequences,
[A:B]
correspondingly.
CY7C1355B
CY7C1357B
Page 10 of 32
s