M29F200BB70N6T NUMONYX, M29F200BB70N6T Datasheet - Page 13

IC FLASH 2MBIT 70NS 48TSOP

M29F200BB70N6T

Manufacturer Part Number
M29F200BB70N6T
Description
IC FLASH 2MBIT 70NS 48TSOP
Manufacturer
NUMONYX
Datasheet

Specifications of M29F200BB70N6T

Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
2M (256K x 8 or 128K x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1707-2

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Part Number:
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Part Number:
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0
M29F200BT, M29F200BB
3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See
Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
ac
125°C), for details of when the output becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See
Table 13
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
impedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at V
Current, I
I
Table 11: DC characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
CC3
waveforms, and
, Chip Enable should be held within V
and
CC2
. To further reduce the Supply Current to the CMOS Standby Supply Current,
Table
IH
. The Data Inputs/Outputs will output the value, see
CC4
Table 12: Read ac characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to
14, Write ac characteristics, for details of the timing requirements.
, for Program or Erase operations until the operation completes.
IH
the Supply Current is reduced to the TTL Standby Supply
IH
, the Data Inputs/Outputs pins are placed in the high-
IL
, to Chip Enable and Output Enable and keeping Write
CC
Figure 9
± 0.2V. For Standby current levels see
and
Figure
Table 2
10, Write ac waveforms, and
125°C).
and
Figure 8: Read Mode
Table
Bus operations
3, Bus
13/39
IH
IH
,
.

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