CY7C1339B-100AC Cypress Semiconductor Corp, CY7C1339B-100AC Datasheet - Page 7
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CY7C1339B-100AC
Manufacturer Part Number
CY7C1339B-100AC
Description
IC SRAM 4MBIT 100MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1339B-100AC.pdf
(17 pages)
Specifications of CY7C1339B-100AC
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4M (128K x 32)
Speed
100MHz
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1092
Document #: 38-05141 Rev. *A
Write Cycle Descriptions
Read
Read
Write Byte 0 – DQ
Write Byte 1 – DQ
Write Bytes 1, 0
Write Byte 2 – DQ
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQ
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
Notes:
4.
5.
6.
X = “don't care,” 1 = Logic HIGH, 0 = Logic LOW.
The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the Write cycle.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
[23:16]
[31:24]
Function
[15:8]
[7:0]
[4, 5, 6]
GW
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
BWE
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BW
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
3
[3:0].
Writes may occur only on subsequent clocks
BW
X
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
2
BW
CY7C1339B
X
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Page 7 of 17
BW
X
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0