MT41J256M8JE-15E:A Micron Technology Inc, MT41J256M8JE-15E:A Datasheet - Page 24
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MT41J256M8JE-15E:A
Manufacturer Part Number
MT41J256M8JE-15E:A
Description
IC DDR3 SDRAM 2GBIT 82FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J256M8JE-15E:A
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
82-FBGA
Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J256M8JE-15E:A
Manufacturer:
MICRON
Quantity:
985
Company:
Part Number:
MT41J256M8JE-15E:A
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Table 5: 96-Ball FBGA – x16 Ball Descriptions (Continued)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
UDQS, UDQS#
LDQS, LDQS#
DQ[15:8]
Symbol
DQ[7:0]
V
V
UDM
V
V
V
REFDQ
REFCA
V
ZQ
NC
DDQ
SSQ
DD
SS
Reference External reference ball for output drive calibration: This ball is tied to an
Supply
Supply
Supply
Supply
Supply
Supply
Type
Input
I/O
I/O
I/O
I/O
–
Description
Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte
input data is masked when UDM is sampled HIGH along with that input data during a
WRITE access. Although the UDM ball is input-only, the UDM loading is designed to
match that of the DQ and DQS balls. UDM is referenced to V
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to V
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to V
Lower byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. Center-aligned to write data.
Upper byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. DQS is center-aligned to write data.
Power supply: 1.5V ±0.075V.
DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity.
Reference voltage for control, command, and address: V
tained at all times (including self refresh) for proper device operation.
Reference voltage for data: V
refresh) for proper device operation.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
external 240Ω resistor (RZQ), which is tied to V
No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
24
REFDQ
REFDQ
REFDQ
.
.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
must be maintained at all times (excluding self
2Gb: x4, x8, x16 DDR3 SDRAM
SSQ
.
© 2006 Micron Technology, Inc. All rights reserved.
REFDQ
REFCA
.
must be main-
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