MT41J256M8JE-15E:A Micron Technology Inc, MT41J256M8JE-15E:A Datasheet - Page 145

• Manufacturer Part Number: MT41J256M8JE-15E:A
• Description: IC DDR3 SDRAM 2GBIT 82FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8JE-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 59: Multipurpose Register (MPR) Block Diagram
Table 76: MPR Functional Description of MR3 Bits
MPR Functional Description
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
MR3[2]
MPR
0
1
(see Table 77 (page 146))
MPR READ Function
“Don’t Care”
Notes:
MR3[1:0]
A[1:0]
The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,
DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining
DQ driven LOW, or for all DQ to output the MPR data . The MPR readout supports fixed
READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ laten-
cies and AC timings applicable, provided the DLL is locked as required.
MPR addressing for a valid MPR read is as follows:
• A[1:0] must be set to 00 as the burst order is fixed per nibble
• A2 selects the burst order:
• For burst chop 4 cases, the burst order is switched on the nibble base along with the
– BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7
following:
– A2 = 0; burst order = 0, 1, 2, 3
– A2 = 1; burst order = 4, 5, 6, 7
Memory core
1. A predefined data pattern can be read out of the MPR with an external READ command.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When
the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.
DQ, DM, DQS, DQS#
MR3[2] = 1 (MPR on)
Normal operation, no MPR transaction
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2
MR3[2] = 0 (MPR off)
145
predefined data for READs
Multipurpose register
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Function
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 3 (MR3)
© 2006 Micron Technology, Inc. All rights reserved.