IS24C02D-2GLI ISSI, Integrated Silicon Solution Inc, IS24C02D-2GLI Datasheet - Page 5

• Manufacturer Part Number: IS24C02D-2GLI
• Description: IC EEPROM 2KBIT 1MHZ 8SOIC
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS24C02D-2GLI

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS24C02D
8-Pin DIP, SOIC, TSSOP, MSOP
PIn DESCRIPTIOnS
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an
open drain output and can be wire Or'ed with other open
drain or open collector outputs. The SDA bus requires a
pullup resistor to Vcc.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that
are hardwired or left unconnected for hardware flexibility.
When pins are hardwired, as many as eight devices may
be addressed on a single bus system. When the pins are
not hardwired, the default values of A0, A1, and A2 are
zero.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
07/30/09
PIN CONFIGURATION
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
GND
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-pad Dfn
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software write-
protection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device.If the device has already received a write-protection
command, the memory in the range of 00h-7Fh is read
-only regardless of the setting of the WP pin.
DEVICE OPERATIOn
The IS24C02D features a serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I
2-WIRE bUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and
the receiving device as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C02D is the Slave device on the bus.
WP
2
C
TM
.
GND
A0
A1
A2
1
2
3
4
(Top View)
8
7
6
5
VCC
WP
SCL
SDA
5