MT47H256M4BT-3:A Micron Technology Inc, MT47H256M4BT-3:A Datasheet - Page 68
![IC DDR2 SDRAM 1GBIT 3NS 92FBGA](/photos/7/26/72643/557-92-fbga_sml.jpg)
MT47H256M4BT-3:A
Manufacturer Part Number
MT47H256M4BT-3:A
Description
IC DDR2 SDRAM 1GBIT 3NS 92FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H256M4HQ-5EE_TR.pdf
(131 pages)
Specifications of MT47H256M4BT-3:A
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (256M x 4)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
92-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H256M4BT-3:A
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Commands
Truth Tables
Table 36: Truth Table – DDR2 Commands
Notes: 1–3 apply to the entire table
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Function
LOAD MODE
REFRESH
SELF REFRESH entry
SELF REFRESH exit
Single bank
PRECHARGE
All banks PRECHARGE
Bank ACTIVATE
WRITE
WRITE with auto
precharge
READ
READ with auto
precharge
NO OPERATION
Device DESELECT
Power-down entry
Power-down exit
Notes:
Previous
Cycle
The following tables provide a quick reference of available DDR2 SDRAM commands,
including CKE power-down modes and bank-to-bank commands.
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at
2. The state of ODT does not affect the states described in this table. The ODT function is
3. “X” means “H or L” (but a defined logic level) for valid I
4. BA2 is only applicable for densities ≥1Gb.
5. An n is the most significant address bit for a given density and configuration. Some larg-
CKE
the rising edge of the clock.
not available during self refresh. See ODT Timing (page 125) for details.
er address bits may be “Don’t Care” during column addressing, depending on density
and configuration.
Current
Cycle
H
H
H
H
H
H
H
H
H
H
X
X
H
L
L
CS#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS#
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
68
X
H
H
H
H
H
X
X
H
X
H
L
L
L
L
L
L
L
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WE#
H
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
1Gb: x4, x8, x16 DDR2 SDRAM
BA2–
BA0
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
An–A11
Column
Column
Column
Column
address
address
address
address
DD
X
X
X
X
X
X
X
X
X
measurements.
© 2004 Micron Technology, Inc. All rights reserved.
Row address
OP code
A10
X
X
X
H
H
H
X
X
X
X
L
L
L
Column
Column
Column
Column
address
address
address
address
Commands
A9–A0 Notes
X
X
X
X
X
X
X
X
X
4, 5, 6,
4, 5, 6,
4, 5, 6,
4, 5, 6,
4, 6
4, 7
6
4
8
8
8
8
9
9
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