MT46V64M8P-5B:D Micron Technology Inc, MT46V64M8P-5B:D Datasheet - Page 51

• Manufacturer Part Number: MT46V64M8P-5B:D
• Description: IC DDR SDRAM 512MBIT 5NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V64M8P-5B:D

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 25:
ACTIVE
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
Extended Mode Register Definition
Notes:
1. n is the most significant row address bit from Table 2 on page 2.
2. The reduced drive strength option is available only on the x16 version. The reduced drive
3. The QFC# option is not supported.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.7 clocks rounded to 3. This is reflected in Figure 26 on page 52, which covers
any case where 2 <
same procedure is used to convert other specification limits from time units to clock
cycles).
A row remains active (or open) for accesses until a PRECHARGE command is issued to
that bank. A PRECHARGE command must be issued before opening a different row in
the same bank.
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
Mn+2
0
0
1
1
strength option is not supported on the x4 and x8 versions; contact Micron for future sup-
port of this feature.
Mn+1
En
0
–
0
1
0
1
n+2
0
BA1 BA0
...
Mode Register Definition
Base mode register
Extended mode register
Reserved
Reserved
0
–
n+1
1
E9
0
–
E8
n 1
0
–
An
E7
t
0
–
RCD (MIN)/
...
...
Operating Mode
E6 E5
0
–
9
A9
t
RCD specification of 20ns with a 133 MHz clock (7.5ns period)
0
–
8
A8
E4
0
–
7
51
A7 A6 A5 A4 A3
E3
0
–
t
6
CK ≤ 3 (Figure 26 also shows the same case for
t
E2
RCD specification.
0
–
E1
3
0
1
5
2
4
E1,
Valid
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Drive Strength
–
E0
3
Reduced
Normal
E0
0
1
2
A2 A1 A0
DS
Operating Mode
Reserved
Reserved
512Mb: x4, x8, x16 DDR SDRAM
1
DLL
0
Disable
Enable
DLL
t
RCD (MIN) should be divided by
Address Bus
Extended Mode
Register (Ex)
©2000 Micron Technology, Inc. All rights reserved.
Operations
t
RRD; the
t
RC.