MT46V64M8P-5B:D Micron Technology Inc, MT46V64M8P-5B:D Datasheet - Page 38

• Manufacturer Part Number: MT46V64M8P-5B:D
• Description: IC DDR SDRAM 512MBIT 5NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V64M8P-5B:D

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 28:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
Any
Idle
Row activating,
active, or
precharging
Read (auto-
precharge
disabled)
Write (auto-
precharge
disabled)
Read
(with auto-
precharge)
Write
(with auto-
precharge)
Current State
Truth Table 4 – Current State Bank n – Command to Bank m
Notes: 1–6 apply to entire table; Notes appear below
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
1. This table applies when CKE
H
H
H
H
X
H
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
valid state for precharging.
bank.
precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
after
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when
• Accessing mode register: Starts with registration of a LOAD MODE REGISTER command
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
CAS#
is met. Once
and ends when
all banks idle state.
t
RP is met. Once
t
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
XSNR has been met (if the previous state was self refresh).
WE#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
t
RFC is met, the DDR SDRAM will be in the all banks idle state.
t
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
MRD has been met. Once
t
RP is met, all banks will be in the idle state.
n-1
38
was HIGH and CKE
Command/Action
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
MRD is met, the DDR SDRAM will be in the
512Mb: x4, x8, x16 DDR SDRAM
n
is HIGH (see Table 30 on page 40) and
©2000 Micron Technology, Inc. All rights reserved.
Commands
Notes
7, 9
7, 8
7, 9
7
7
7
7
7
7
7
t
RFC