MT45W2MW16PABA-70 WT Micron Technology Inc, MT45W2MW16PABA-70 WT Datasheet

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... AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ASYNC/PAGE CellularRAM MEMORY MT45W2MW16PAFA MT45W2ML16PAFA TM A ...

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... ASYNC/PAGE CellularRAM MEMORY To operate seamlessly on an asynchronous memory bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory con- troller and has no significant impact on device read/ write performance. Special attention has been focused on current con- sumption during self refresh ...

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... DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled. 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY DESCRIPTION Address Inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the CR. On the 16Mb device, A20 (ball H6) is not internally connected ...

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... PART NUMBER MT45W2MW16PAFA-85 WT MT45W2MW16PAFA-70 WT MT45W2ML16PAFA-85 WT MT45W2ML16PAFA-70 WT MT45W1MW16PAFA-85 WT MT45W1MW16PAFA-70 WT MT45W1ML16PAFA-85 WT MT45W1ML16PAFA-70 WT 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ASYNC/PAGE CellularRAM MEMORY ENGINEERING SAMPLE PX400 PX401 PX403 PX404 PX104 PX105 PX107 PX108 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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... MT45W1Mx16PA contains 16,777,216 bits organized as 1,048,576 addresses by 16 bits. These devices include the industry-standard, asyn- chronous memory interface found on other low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. ...

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... DON’T CARE to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is abso- lutely necessary. The refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. Data stored in addresses not receiving refresh will become corrupted ...

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... AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ASYNC/PAGE CellularRAM MEMORY Driving the ZZ# pin LOW will place the device in the PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using CR software access ...

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... ZZ# 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ASYNC/PAGE CellularRAM MEMORY Software Access to the Configuration Register The contents of the CR can either be read or modi- fied using a software sequence. The nature of this access mechanism may eliminate the need for the ZZ# pin ...

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... Figure 10: Software Access Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA NOTE: CE# must be HIGH for 150ns before performing the cycle that reads the configuration register. 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY READ READ WRITE ADDRESS ADDRESS ADDRESS (MAX) (MAX) (MAX) XXXXh ...

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... Partial Array Refresh (CR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the sys- tem to reduce current by only refreshing that part of the memory array required by the host system. The refresh options are full array, three-quarters array, one- half array, one-quarter array, or none of the array ...

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... Address Patterns for PAR (CR[ CR[2] CR[1] CR[ 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY PAGE SLEEP RESERVED TCR Must be set to "0" Sleep Mode CR[4] DPD Enabled 0 PAR Enabled (default) 1 ACTIVE SECTION ADDRESS SPACE Full die 000000h–1FFFFFh Three-quarters of die 000000h–2FFFFFh One-half of die 000000h–1FFFFFh One-quarter of die 000000h– ...

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... PAR set to FULL ARRAY and TCR set to +85°C. In order to achieve low standby cur- SB rent, all inputs must be driven to V 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY Q *Stresses greater than those listed under “Absolute CC Maximum Ratings” may cause permanent damage to the device ...

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... IN CC Current ZZ CR[ NOTE: I (MAX) values measured with TCR set to 85°C. PAR Table 10: Deep Power-Down Specifications and Conditions DESCRIPTION Deep Power-Down 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY SYMBOL POWER Q or 0V, I 32Mb TCR Q Standard CC (no desig.) 32Mb Low-power option (L) ...

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... CC 2. Input timing begins at V /2. Due to the possibility of a difference between V CC not be shown to scale. 3. Output timing ends at V Q/2. CC Figure 12: Output Load Circuit VccQ R1 DUT 30pF R2 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY CONDITIONS SYMBOL T = +25º MHz Test Points CC for a logic 0. Input rise and fall times (10% to 90%) < ...

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... High-Z to Low-Z timings are tested with the circuit shown in Figure 12 on page 14. The Low-Z timings measure a 100mV transition away from the High Low-Z to High-Z timings are tested with the circuit shown in Figure 12 on page 14. The High-Z timings measure a 100mV transition from either V OH 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY -70 SYMBOL MIN ...

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... Chip Deselect to ZZ# LOW Deep Power-Down Recovery Minimum ZZ# Pulse Width TIMING DIAGRAMS Figure 13: Power-Up Initialization Period Vcc, VccQ = 1.7V Table 17: Power-Up Initialization Timing Requirements PARAMETER Power-Up Initialization Period 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ASYNC/PAGE CellularRAM MEMORY -70 SYMBOL MIN MAX ...

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... Figure 14: Load Configuration Register ADDRESS LB#/UB# Table 18: Load Configuration Register Timing Requirements -70 SYMBOL MIN MAX MIN CDZZ 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY t WC OPCODE CE WE# OE CDZZ ZZWE ZZ# -85 MAX UNITS SYMBOL ZZWE 17 2 MEG x 16, 1 MEG DON’T CARE ...

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... ZZ (MIN) ZZ# CE# Table 19: Deep Power-Down Timing Parameters SYMBOL t CDZZ (MIN) 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ASYNC/PAGE CellularRAM MEMORY t R -70 MIN MAX MIN 5 5 150 150 10 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 ...

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... Figure 16: Single READ Operation (WE ADDRESS LB#/UB# DATA-OUT Table 20: READ Timing Parameters -70 SYMBOL MIN MAX MIN BHZ t 10 BLZ 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY t RC ADDRESS VALID BLZ t OE OE# t OLZ High-Z DON’T CARE -85 MAX UNITS SYMBOL OHZ ...

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... A[3:0] CE# LB#/UB# OE# DATA-OUT Table 21: Page Mode READ Timing Parameters -70 SYMBOL MIN MAX MIN APA BHZ t 10 BLZ 10 t CEM 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY t RC ADDRESS VALID CEM BLZ OLZ t DATA DATA High-Z VALID VALID -85 MAX UNITS SYMBOL ...

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... Figure 18: WRITE Cycle (WE# Control) ADDRESS LB#/UB# DATA-IN DATA-OUT Table 22: WRITE Timing Parameters -70 SYMBOL MIN MAX MIN CEM 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY t WC ADDRESS VALID CEM WE# OE# t WHZ -85 MAX UNITS SYMBOL WHZ 10 µ WPH MEG x 16, 1 MEG x 16 ...

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... Figure 19: WRITE Cycle (CE# Control) ADDRESS LB#/UB# DATA-IN DATA-OUT Table 23: WRITE Timing Parameters -70 SYMBOL MIN MAX MIN CEH 10 t CEM 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY CEM WE# OE WHZ -85 MAX UNITS SYMBOL WHZ 10 µ MEG x 16, 1 MEG CEH Data Valid High-Z DON’ ...

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... Figure 20: WRITE Cycle (LB#/UB# Control) ADDRESS CE# LB#/UB# WE# OE# DATA-IN DATA-OUT Table 24: WRITE Timing Parameters -70 SYMBOL MIN MAX MIN CEM 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY CEM WHZ -85 MAX UNITS SYMBOL µs t WHZ MEG x 16, 1 MEG Data Valid High-Z DON’T CARE ...

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... Micron, and the Micron and M Logos are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc. inside the U.S. and a trademark of Infineon Technologies outside the U.S. All other trademarks are the property of their respective owners. 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY Figure 21: 48-Ball FBGA 3.75 0.75 TYP ...

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... PAGE MODE TIMING CONSTRAINT Disabled t CEM and (See Figures 22 and 23 above.) Enabled t CEM > 10µs (See Figure 22 above.) 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY Figure 22: Extended Timing for Figure 23: Extended Timing for t CEM READ CYCLE t No impact. TM > 10µ MEG x 16, 1 MEG < ...

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... WRITE cycle time ( [MIN]). These increased timings ensure that time is available for both a refresh operation and a successful completion of the WRITE operation. 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM MEMORY Figure 24: Extended WRITE Operation ADDRESS CE# LB#/UB# WE# DATA-IN ...

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... Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03 • Initial Release 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ASYNC/PAGE CellularRAM MEMORY • Added on-chip sensor to TCR. • Clarified software access description. Micron Technology, Inc., reserves the right to change products or specifications without notice. 27 ADVANCE ©2004 Micron Technology, Inc. All Rights Reserved. ...