MT46V32M4P-5B:D TR Micron Technology Inc, MT46V32M4P-5B:D TR Datasheet - Page 39
MT46V32M4P-5B:D TR
Manufacturer Part Number
MT46V32M4P-5B:D TR
Description
IC DDR SDRAM 128MBIT 5NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V16M8TG-6T_LD_TR.pdf
(81 pages)
Specifications of MT46V32M4P-5B:D TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (32Mx4)
Speed
5ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 39 of 81
- Download datasheet (7Mb)
ACTIVE (ACT)
Figure 15:
READ
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
Activating a Specific Row in a Specific Bank
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access, like a read or a write, as shown in Figure 15. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0–An selects the row.
The READ command is used to initiate a burst read access to an active row, as shown in
Figure 16 on page 40. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–Ai (where Ai is the most significant column address bit for a given
density and configuration, see Table 2 on page 2) selects the starting column location.
BA0, BA1
ADDRESS
RAS#
CAS#
WE#
CK#
CKE
CS#
CK
HIGH
DON’T CARE
Bank
Row
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
©2004 Micron Technology, Inc. All rights reserved.
Commands
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