MT46V32M4P-5B:D TR Micron Technology Inc, MT46V32M4P-5B:D TR Datasheet - Page 51
![IC DDR SDRAM 128MBIT 5NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V32M4P-5B:D TR
Manufacturer Part Number
MT46V32M4P-5B:D TR
Description
IC DDR SDRAM 128MBIT 5NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V16M8TG-6T_LD_TR.pdf
(81 pages)
Specifications of MT46V32M4P-5B:D TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (32Mx4)
Speed
5ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 29 on page 56. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 30 on page 57. The
t
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 31 on page 58. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both
and
last data elements.
DQSS (MAX) case has a longer bus idle time. (
t
RP have been met. Part of the row precharge time is hidden during the access of the
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
128Mb: x4, x8, x16 DDR SDRAM
DQSS [MIN] and
t
DQSS (NOM) case is shown; the
©2004 Micron Technology, Inc. All rights reserved.
t
DQSS [MAX] are
Operations
t
RAS
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