AT49SV322DT-80TU Atmel, AT49SV322DT-80TU Datasheet - Page 12

• Manufacturer Part Number: AT49SV322DT-80TU
• Description: IC FLASH 32MBIT 80NS 48TSOP
• Manufacturer: Atmel

Specifications of AT49SV322DT-80TU

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (2M x 16)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. Command Definition Table
Notes:
12
Command
Sequence
Read
Chip Erase
Sector Erase
Word Program
Dual Word
Program
Enter Single Pulse
Program Mode
Single Pulse Word
Program
Sector Lockdown
Erase/Program
Suspend
Erase/Program
Resume
Product ID Entry
Product ID Exit
Product ID Exit
Program Protection
Register
Lock Protection
Register - Block B
Status of Block B
Protection
Set Configuration
Register
CFI Query
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages
4. This fast programming option enables the user to program two words in parallel only when V
5. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or
6. Either one of the Product ID Exit commands can be used.
7. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
8. Any addresses within the user programmable protection register region. Address locations are shown on
9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
10. The default state (after power-up) of the configuration register is “00”.
11. When accessing the data in the CFI table, the address format is A15 - A0 (Hex).
(4)
(11)
AT49SV322D(T)
FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are don’t care.
details).
Addr0 and Addr1, of the two words, D
manufacturing purposes only.
power cycled.
ter Addressing Table” on page
(6)
(6)
Cycles
Bus
1
1
6
6
4
5
6
1
6
1
1
3
3
1
4
4
4
4
Addr
X55
Addr
Addr
XXX
XXX
XXX
555
555
555
555
555
555
555
555
555
555
555
555
1st Bus
Cycle
Data
D
F0
98
D
AA
AA
AA
AA
AA
AA
B0
AA
AA
AA
AA
AA
AA
30
OUT
IN
(7)
13.
AAA
AAA
Addr
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
IN0
2nd Bus
Cycle
(2)
(2)
and D
Data
IN1
55
55
55
55
55
55
55
55
55
55
55
55
, must only differ in address A0. This command should be used during
Addr
555
555
555
555
555
555
555
555
555
555
555
555
3rd Bus
Cycle
Data
F0
A0
E0
C0
C0
D0
80
80
80
80
90
90
(7)
Addr
Addr
Addr0
Addr
XXX
555
555
555
555
080
80
(8)
4th Bus
Cycle
00/01
D
Data
D
OUT
D
D
AA
AA
AA
AA
X0
IN0
IN
IN
(9)
(10)
Addr
Addr1
AAA
AAA
AAA
AAA
PP
5th Bus
= 9.5V. The Addresses,
Cycle
Data
D
55
55
55
55
IN1
“Protection Regis-
3623A–FLASH–7/06
SA
Addr
SA
555
555
(3)(5)
6th Bus
(3)
14
Cycle
-
17
Data
A0
10
30
60
for