AT25128A-10TU-1.8 Atmel, AT25128A-10TU-1.8 Datasheet - Page 9

• Manufacturer Part Number: AT25128A-10TU-1.8
• Description: IC EEPROM 128KBIT 20MHZ 8TSSOP
• Manufacturer: Atmel

Specifications of AT25128A-10TU-1.8

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 5MHz, 10MHz, 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Functional Description
3368J–SEEPR–06/07
The AT25128A/256A is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and their opera-
tion codes are contained in see
with the MSB first and start with a high-to-low CS transition.
Table 3-1.
WRITE ENABLE (WREN): The device will power-up in the write disable state when V
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The Ready/Busy and Write Enable status of the device can be determined by
the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruction.
Table 3-2.
Table 3-3.
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4  6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN)
Bits 0  7 are “1”s during an internal write cycle.
WPEN
Bit 7
Instruction Set for the AT25128A/256A
Status Register Format
Read Status Register Bit Definition
Bit 6
X
Definition
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 = 0 indicates the device is not write enabled. Bit 1 = “1” indicates
the device is write enabled.
See
See
See
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Table 3-4 on page 10
Table 3-4 on page 10
Table 3-5 on page 10
Bit 5
X
Table
Bit 4
X
4-3. All instructions, addresses, and data are transferred
Bit 3
.
.
.
BP1
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bit 2
BP0
AT25128A_256A
WEN
Bit 1
Bit 0
RDY
CC
is
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