AT45DB642-TI Atmel, AT45DB642-TI Datasheet - Page 2

• Manufacturer Part Number: AT45DB642-TI
• Description: IC FLASH 64MBIT 20MHZ 40TSOP
• Manufacturer: Atmel

Specifications of AT45DB642-TI

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 20MHz Serial/5MHz Parallel
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Block Diagram
Memory Array
2
AT45DB642
However, the use of either interface is purely optional. Its 69,206,016 bits of memory are orga-
nized as 8192 pages of 1056 bytes each. In addition to the main memory, the AT45DB642
also contains two SRAM data buffers of 1056 bytes each. The buffers allow receiving of data
while a page in the main memory is being reprogrammed, as well as reading or writing a con-
tinuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-
contained three step Read-Modify-Write operation. Unlike conventional Flash memories that
are accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses either a serial interface or a parallel interface to sequentially access its data. The simple
sequential access facilitates hardware layout, increases system reliability, minimizes switching
noise, and reduces package size and active pin count. DataFlash supports SPI mode 0 and
mode 3. The device is optimized for use in many commercial and industrial applications where
high-density, low-pin count, low-voltage, and low-power are essential. The device operates at
clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the AT45DB642 does not require high input
voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for
both the program and read operations. The AT45DB642 is enabled through the chip select pin
(CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output
(SO), and the Serial Clock (SCK), or a parallel interface consisting of the parallel input/output
pins (I/O7 - I/O0) and the clock pin (CLK). The SCK and CLK pins are shared and provide the
same clocking input to the DataFlash.
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory array may
not be erased. In other words, the contents of the last page may not be filled with FFH.
To provide optimal flexibility, the memory array of the AT45DB642 is divided into three levels
of granularity comprising of sectors, blocks and pages. The “Memory Architecture Diagram”
illustrates the breakdown of each level and details the number of pages per sector and block.
All program operations to the DataFlash occur on a page-by-page basis; however, the optional
erase operations can be performed at the block or page level.
RDY/BUSY
SER/PAR
SCK/CLK
RESET
GND
VCC
WP
CS
PAGE (1056 BYTES)
BUFFER 1 (1056 BYTES)
SI
SO
FLASH MEMORY ARRAY
I/O INTERFACE
BUFFER 2 (1056 BYTES)
I/O7 - I/O0
1638F–DFLSH–09/02
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