AT49BV4096A-12RI Atmel, AT49BV4096A-12RI Datasheet - Page 5
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AT49BV4096A-12RI
Manufacturer Part Number
AT49BV4096A-12RI
Description
IC FLASH 4MBIT 120NS 44SOIC
Manufacturer
Atmel
Datasheet
1.AT49BV4096A-12RC.pdf
(16 pages)
Specifications of AT49BV4096A-12RI
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8 or 256K x 16)
Speed
120ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
44-SOIC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV004(T)/4096A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.
T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e
AT49BV004(T)/4096A(T) provides another method for
determining the end of a program or erase cycle. During a
program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
READY/BUSY: For the AT49BV004(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase opera-
tion. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the comple-
tion of the cycle. The open drain connection allows for OR-
tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e
AT49BV004(T)/4096A(T) in the following ways: (a) V
sense: if V
is inhibited. (b) V
the V
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
CC
sense level, the device will automatically time out
CC
is below 1.8V (typical), the program function
CC
power on delay: once V
CC
+ 0.6V.
CC
has reached
CC
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