AT45DB642-TC Atmel, AT45DB642-TC Datasheet - Page 8

• Manufacturer Part Number: AT45DB642-TC
• Description: IC FLASH 64MBIT 20MHZ 40TSOP
• Manufacturer: Atmel

Specifications of AT45DB642-TC

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 20MHz Serial/5MHz Parallel
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Block Erase Addressing
Additional
Commands
8
PA12
0
0
0
0
1
1
1
1
•
•
•
AT45DB642
PA11
0
0
0
0
1
1
1
1
•
•
•
PA10
0
0
0
0
1
1
1
1
•
•
•
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of
the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations.
Data is first clocked into buffer 1 or buffer 2 from the input pins (SI or I/O7 - I/O0) and then pro-
grammed into a specified page in the main memory. A 1-byte opcode, 82H for buffer 1 or 85H
for buffer 2, must first be clocked into the device, followed by three address bytes. The
address bytes are comprised of 13 page address bits (PA12 - PA0) that select the page in the
main memory where data is to be written, and 11 buffer address bits (BFA10 - BFA0) that
select the first byte in the buffer to be written. After all address bytes are clocked in, the part
will take data from the input pins and store it in the specified data buffer. If the end of the buffer
is reached, the device will wrap around back to the beginning of the buffer. When there is a
low-to-high transition on the CS pin, the part will first erase the selected page in main memory
to all 1s and then program the data stored in the buffer into that memory page. Both the erase
and the programming of the page are internally self-timed and should take place in a maxi-
mum time of t
the part is busy.
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the
main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte opcode, 53H for
buffer 1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes
comprised of 13 page address bits (PA12 - PA0), which specify the page in main memory that
is to be transferred, and 11 don’t care bits. The CS pin must be low while toggling the
SCK/CLK pin to load the opcode and the address bytes from the input pins (SI or I/O7 - I/O0).
The transfer of the page of data from the main memory to the buffer will begin when the CS pin
transitions from a low to a high state. During the transfer of a page of data (t
register can be read or the RDY/BUSY can be monitored to determine whether the transfer
has been completed.
PA9
0
0
0
0
1
1
1
1
•
•
•
PA8
0
0
0
0
1
1
1
1
•
•
•
EP
. During this time, the status register and the RDY/BUSY pin will indicate that
PA7
0
0
0
0
1
1
1
1
•
•
•
PA6
0
0
0
0
1
1
1
1
•
•
•
PA5
0
0
0
0
1
1
1
1
•
•
•
PA4
0
0
1
1
0
0
1
1
•
•
•
PA3
0
1
0
1
0
1
0
1
•
•
•
PA2
X
X
X
X
X
X
X
X
•
•
•
PA1
X
X
X
X
X
X
X
X
•
•
•
PA0
X
X
X
X
X
X
X
X
XFR
1638F–DFLSH–09/02
•
•
•
), the status
Block
1020
1021
1022
1023
0
1
2
3
•
•
•