28C64A-20/P Microchip Technology, 28C64A-20/P Datasheet - Page 6

• Manufacturer Part Number: 28C64A-20/P
• Description: IC EEPROM 64KBIT 200NS 28DIP
• Manufacturer: Microchip Technology

Specifications of 28C64A-20/P

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 200ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

28C64A
2.0
The Microchip Technology Inc.
modes of operation—read, standby, write inhibit, and
byte write—as outlined in the following table.
2.1
The
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to the
output pins independent of device selection. Assuming
that addresses are stable, address access time (tACC)
is equal to the delay from CE to output (tCE). Data is
available at the output t
assuming that CE has been low and addresses have
been stable for at least t
2.2
The
a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.
2.3
In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal V
the initiation of non-volatile programming operation
when V
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10 ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (V
DS11109K-page 6
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
Note 1: Open drain output.
Operation
Mode
28C64A
28C64A
2: X = Any TTL level.
CC
DEVICE OPERATION
Read Mode
Standby Mode
Data Protection
is less than the V
is placed in the standby mode by applying
has two control functions, both of which
CE
H
H
X
X
L
L
CC
Automatic Before Each “Write”
OE
detect (3.3 volts typical) will inhibit
X
X
X
H
L
L
OE
ACC
WE
after the falling edge of OE,
H
H
X
X
X
L
-t
CC
OE
detect circuit trip.
28C64A
.
High Z
High Z
High Z
High Z
D
D
I/O
OUT
IN
CC
has four basic
).
Rdy/Busy
(1)
H
H
H
H
H
L
2.4
The
RAM. The write cycle is completely self-timed and ini-
tiated by a low going pulse on the WE pin. On the fall-
ing edge of WE, the address information is latched. On
rising edge, the data and the control pins (CE and OE)
are latched. The Ready/Busy pin goes to a logic low
level indicating that the
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the
to accept another cycle.
2.5
The
tion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 are indetermin-
able). After completion of the write cycle, true data is
available. Data polling allows a simple read/compare
operation to determine the status of the chip eliminating
the need for external hardware.
2.6
An extra row of 32 bytes of EEPROM memory is avail-
able to the user for device identification. By raising A9
to 12V 0.5V and using address locations 1FEO to
1FFF, the additional bytes can be written to or read
from in the same manner as the regular memory array.
2.7
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.
28C64A
28C64A
Write Mode
Data Polling
Electronic Signature for Device
Identification
Chip Clear
28C64A
features Data polling to signal the comple-
has a write cycle similar to that of a Static
has completed writing and is ready
28C64A
2004 Microchip Technology Inc.
is in a write cycle which