CAT25128LI-G ON Semiconductor, CAT25128LI-G Datasheet - Page 8

• Manufacturer Part Number: CAT25128LI-G
• Description: IC EEPROM 128KBIT 10MHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT25128LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Density: 128Kb
• Interface Type: Serial (SPI)
• Organization: 16Kx8
• Access Time (max): 75ns
• Frequency (max): 5MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temp Range: -40C to 85C
• Supply Current: 4mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Maximum Clock Frequency: 10 MHz
• Access Time: 75 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 25128LI-G

Write Status Register
instruction according to timing shown in Figure 7. Only bits
2, 3 and 7 can be written using the WRSR command.
SCK
SO
CS
The Status Register is written by sending a WRSR
SI
Dashed Line = mode (1, 1)
SCK
WP
WP
CS
Dashed Line = mode (1, 1)
0
0
0
1
HIGH IMPEDANCE
0
2
0
3
OPCODE
0
4
0
5
Figure 7. WRSR Timing
Figure 8. WP Timing
0
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6
1
7
8
t
WPS
MSB
7
8
Write Protection
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
The Write Protect (WP) pin can be used to protect the
t
9
6
WPH
10
5
11
4
DATA IN
12
3
13
2
14
1
15
0