X28HC64JIZ-90 Intersil, X28HC64JIZ-90 Datasheet - Page 5

• Manufacturer Part Number: X28HC64JIZ-90
• Description: IC EEPROM 64KBIT 90NS 32PLCC
• Manufacturer: Intersil

Specifications of X28HC64JIZ-90

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Toggle Bit I/O
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC64 memories that is frequently
updated. Toggle Bit Polling can also provide a method for
status checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on the
bus. The software flow diagram in Figure 5 illustrates a
method for polling the Toggle Bit.
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
I/O
WE
OE
CE
6
WRITE
* BEGINNING AND ENDING STATE OF I/O
LAST
FROM ADDR N
LOAD ACCUM
ACCUM WITH
COMPARE
LAST WRITE
COMPARE
READY
ADDR N
OK?
YES
YES
6
5
*
NO
V
OH
FIGURE 4. TOGGLE BIT BUS SEQUENCE
6
WILL VARY.
V
OL
X28HC64
HIGH Z
Hardware Data Protection
The X28HC64 provides two hardware features that protect
nonvolatile data from inadvertent writes.
• Default V
• Write Inhibit—Holding either OE LOW, WE HIGH, or CE
Software Data Protection
The X28HC64 offers a software controlled data protection
feature. The X28HC64 is shipped from Intersil with the software
data protection NOT ENABLED; that is, the device will be in the
standard operating mode. In this mode data should be
protected during power-up/-down operations through the use of
external circuits. The host would then have open read and write
access of the device once V
The X28HC64 can be automatically protected during power-
up and power-down without the need for external circuits by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation utilizing the software algorithm. This circuit is
nonvolatile and will remain set for the life of the device,
unless the reset command is issued.
Once the software protection is enabled, the X28HC64 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figure 6 and 7 for the sequence. The three-byte sequence
opens the page write window, enabling the host to write from
one to sixty-four bytes of data. Once the page load cycle has
been completed, the device will automatically be returned to
the data protected state.
V
HIGH will prevent an inadvertent write cycle during power-
up and power-down, maintaining data integrity.
CC
is 3V typically.
CC
Sense—All write functions are inhibited when
*
CC
was stable.
X28HC64
READY
August 28, 2009
FN8109.2