X28HC64J-70 Intersil Corporation, X28HC64J-70 Datasheet
X28HC64J-70
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X28HC64J-70 Summary of contents
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Data Sheet 5 Volt, Byte Alterable EEPROM FEATURES • 70ns access time • Simple byte and page write —Single 5V supply —No external high voltages or V —Self-timed —No erase before write —No complex programming algorithms —No overerase problem ...
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... Ordering Information PART NUMBER PART MARKING X28HC64EM-70 X28HC64EM-70 X28HC64J-70 X28HC64J-70* X28HC64JI-70 X28HC64JI-70* X28HC64JI-70 Z X28HC64JIZ-70* (Note) X28HC64J-70 Z X28HC64JZ-70* (Note) X28HC64KM-70 X28HC64KM-70 X28HC64P-70 X28HC64P-70 X28HC64P-70 Z X28HC64PZ-70 (Note) X28HC64S-70 X28HC64S-70* X28HC64SI-70 X28HC64SI-70* X28HC64SM-70 X28HC64SM-70* X28HC64S-70 Z X28HC64SZ-70 (Note) X28HC64J-90 X28HC64J-90* X28HC64JI-90 X28HC64JI-90* X28HC64JI-90 Z X28HC64JIZ-90* (Note) ...
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... PART MARKING X28HC64D-12 X28HC64D-12 X28HC64DI-12 X28HC64DI-12 X28HC64DM-12 X28HC64DM-12 X28HC64DMB-12 C X28HC64DMB-12 X28HC64FM-12 X28HC64FM-12 X28HC64J-12* X28HC64J-12 X28HC64JI-12* X28HC64JI-12 X28HC64JIZ-12* (Note) X28HC64JI-12 Z X28HC64JZ-12* (Note) X28HC64J-12 Z X28HC64KMB-12 C X28HC64KMB-12 X28HC64P-12 X28HC64P-12 X28HC64PI-12 X28HC64PI-12 X28HC64PIZ-12 (Note) X28HC64PI-12 Z X28HC64PZ-12 (Note) X28HC64P-12 Z X28HC64S-12* X28HC64S-12 X28HC64SI-12* X28HC64SI-12 X28HC64SIZ-12* (Note) X28HC64SI-12 Z ...
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PIN DESCRIPTIONS Addresses ( The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is ...
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DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus ...
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DATA POLLING I/O 7 Figure 2. DATA Polling Bus Sequence Last Write I – Figure 3. DATA Polling Software Flow Write Data Writes Complete? Yes Save Last Data and ...
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THE TOGGLE BIT I/O 6 Figure 4. Toggle Bit Bus Sequence Last WE Write Beginning and ending state of I/O Figure 5. Toggle Bit Software Flow Last Write Yes Load Accum From Addr N ...
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HARDWARE DATA PROTECTION The X28HC64 provides two hardware features that protect nonvolatile data from inadvertent writes. – Default V Sense—All write functions are inhibited CC when typically. CC – Write Inhibit—Holding either OE LOW, WE HIGH, or ...
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SOFTWARE DATA PROTECTION Figure 6. Timing Sequence—Byte or Page Write Data AAA ADDR 1555 CE WE Figure 7. Write Sequence for Software Data Protection Write Data AA to Address 1555 Write Data 55 to Address 0AAA Write ...
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RESETTING SOFTWARE DATA PROTECTION Figure 8. Reset Software Data Protection Timing Sequence V CC AAA Data 1555 0AAA ADDR CE WE Figure 9. Software Sequence to Deactivate Software Data Protection Write Data AA to Address 1555 Write Data 55 to ...
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SYSTEM CONSIDERATIONS Because the X28HC64 is frequently used in large memory arrays provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipa- tion, and eliminate the possibility ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias X28HC64 ......................................... -10°C to +85°C X28HC64I, X28HC64M .................. -65°C to +135°C Storage temperature.......................... -65°C to +150°C Voltage on any pin with respect to V ......................................... -1V to +7V SS D.C. output current ............................................... 5mA ...
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ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention POWER-UP TIMING Symbol (3) t Power-up to read operation PUR (3) t Power-up to write operation PUW CAPACITANCE T = +25° 1MHz Symbol Parameter (3) C Input/output ...
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A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read Cycle Limits Symbol Parameter t Read cycle time RC t Chip enable access time CE t Address access time AA t Output enable access time OE ( ...
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WRITE CYCLE LIMITS Symbol Parameter (5) t Write cycle time WC t Address setup time AS t Address hold time AH t Write setup time CS t Write hold time pulse width High setup ...
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CE CONTROLLED WRITE CYCLE Address OES Data In Data Out Page Write Cycle ( (8) Address* I/O Byte 0 *For each successive write within the page write ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...