CY7C1371D-100AXI Cypress Semiconductor Corp, CY7C1371D-100AXI Datasheet - Page 18

• Manufacturer Part Number: CY7C1371D-100AXI
• Description: IC SRAM 18MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1371D-100AXI

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 8.5 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 175 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 18Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 175mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3716 - ADAPTER SOCKET PTG
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Identification Register Definitions
Scan Register Sizes
Identification Codes
Document Number: 38-05556 Rev. *I
Revision number (31:29)
Device depth (28:24)
Device width (23:18)
Cypress device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID register presence indicator (0)
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Instruction Field
Register Name
Code
000
001
010
011
100
101
110
111
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
Do Not Use: This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
00000110100
CY7C1371D
(512 K × 36)
001001
100101
01011
000
1
00000110100
CY7C1373D
(1 M × 18)
Bit Size (× 36)
001001
010101
01011
000
1
32
85
89
3
1
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Description
Bit Size (× 18)
32
85
89
3
1
CY7C1371D
CY7C1373D
Page 18 of 33
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