CY14E256LA-SZ45XI Cypress Semiconductor Corp, CY14E256LA-SZ45XI Datasheet - Page 14
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CY14E256LA-SZ45XI
Manufacturer Part Number
CY14E256LA-SZ45XI
Description
IC NVSRAM 256KBIT 45NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Datasheet
1.CY14E256LA-SZ45XI.pdf
(19 pages)
Specifications of CY14E256LA-SZ45XI
Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
256K (32K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Word Size
8b
Organization
32Kx8
Density
256Kb
Interface Type
Parallel
Access Time (max)
45ns
Operating Supply Voltage (typ)
5V
Package Type
SOIC
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
-40C to 85C
Pin Count
32
Mounting
Surface Mount
Supply Current
52mA
Memory Configuration
32K X 8
Access Time
45ns
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY14E256LA-SZ45XI
Manufacturer:
SHARP
Quantity:
22 502
Part Number:
CY14E256LA-SZ45XI
Manufacturer:
CYPRESS
Quantity:
20 000
Part Number:
CY14E256LA-SZ45XIKU
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY14E256LA-SZ45XIT
Manufacturer:
CYPRESS
Quantity:
1 241
Document Number: 001-54952 Rev. *F
Hardware STORE Cycle
Switching Waveforms
t
t
t
Notes
DHSB
PHSB
SS
30. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
31. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
32. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
[30, 31]
Parameter
Write Latch set
HSB (IN)
HSB (OUT)
SO
RWI
Write Latch not set
HSB (IN)
HSB (OUT)
RWI
Address
V
CE
CC
Address #1
t
SA
HSB to output active time when write latch not set
Hardware STORE pulse width
Soft sequence processing time
t DELAY
t DELAY
t PHSB
Soft Sequence
t PHSB
Command
Figure 12. Soft Sequence Processing
Figure 11. Hardware STORE Cycle
Address #6
t DHSB
t
CW
Description
t
SS
t STORE
t DHSB
Address #1
Soft Sequence
Command
HSB pin is driven high to V
100 K resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
[32]
[30, 31]
Address #6
t
CW
t LZHSB
t HHHD
t
SS
Min
CCQ
CY14E256LA
15
–
–
only by Internal
CY14E256LA
Max
100
25
–
Page 14 of 19
Unit
ns
ns
μs
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