PSD834F2-70M STMicroelectronics, PSD834F2-70M Datasheet - Page 35
![IC FLASH 2MBIT 70NS 52QFP](/photos/7/25/72513/497-52-pqfp_series_sml.jpg)
PSD834F2-70M
Manufacturer Part Number
PSD834F2-70M
Description
IC FLASH 2MBIT 70NS 52QFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2VA-20JI.pdf
(109 pages)
Specifications of PSD834F2-70M
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-2005
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD834F2-70M
Manufacturer:
Samsung
Quantity:
6 000
Company:
Part Number:
PSD834F2-70M
Manufacturer:
STMicroelectronics
Quantity:
10 000
Decode PLD (DPLD)
The DPLD, shown in Figure 14, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
■
■
Figure 14. DPLD Logic Array
I /O PORTS (PORT A,B,C)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
PGR0 - PGR7
A [ 15:0 ]
PD [ 2:0 ] (ALE,CLKIN,CSI)
PDN (APD OUTPUT)
CNTRL [ 2:0 ] ( READ/WRITE CONTROL SIGNALS)
RESET
RD_BSY
8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
4 Sector Select (CSBOOT0-CSBOOT3)
signals for the secondary Flash memory (three
product terms each)
*
(INPUTS)
(24)
(16)
(8)
(8)
(8)
(3)
(3)
(1)
(1)
(1)
Doc ID 10552 Rev 3
■
■
■
■
1 internal SRAM Select (RS0) signal (two
product terms)
1 internal CSIOP Select (PSD Configuration
Register) signal
1 JTAG Select signal (enables JTAG on Port
C)
2 internal Peripheral Select signals
(Peripheral I/O mode).
3
3
3
3
3
3
3
3
3
3
3
3
2
1
1
1
1
RS0
CSIOP
PSEL0
PSEL1
JTAGSEL
PSD813F2V, PSD854F2V
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS1
FS7
FS2
FS3
FS5
FS6
FS4
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O MODE
SELECT
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
AI02873D
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