M48Z35AV-10PC1 STMicroelectronics, M48Z35AV-10PC1 Datasheet - Page 8

• Manufacturer Part Number: M48Z35AV-10PC1
• Description: IC NVSRAM 256KBIT 100NS 28DIP
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z35AV-10PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 100ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: PCDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 50mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2882-5

Operating modes
2
Note:
2.1
8/25
Operating modes
The M48Z35AV also has its own power-fail detect circuit. The control circuitry constantly
monitors the single power supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately V
power returns.
Table 2.
1. See
X = V
READ mode
The M48Z35AV is in the READ mode whenever W (WRITE enable) is high, E (chip enable)
is low. The device architecture allows ripple-through access of data from eight of 264,144
locations in the static storage array. Thus, the unique address specified by the 15 address
inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the data I/O pins within address access time (t
signal is stable, providing that the E and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the chip enable
access time (t
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 10 on page 17
or V
V
IL
Operating modes
SO
; V
ELQV
3.0 to 3.6 V
SO
to V
SO
≤ V
AVQV
, the control circuitry connects the battery which maintains data until valid
) or output enable access time (t
V
PFD
= Battery backup switchover voltage.
SO
CC
, the data lines will be driven to an indeterminate state until t
(1)
(min)
for details.
AXQX
(1)
Doc ID 6784 Rev 8
) but will go indeterminate until the next address access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
GLQV
).
DQ0-DQ7
AVQV
High Z
High Z
High Z
High Z
D
D
CC
OUT
IN
) after the last address input
. As V
CC
Battery backup mode
falls below
CMOS standby
CC
Standby
Power
Active
Active
Active
is out of
M48Z35AV
AVQV
. If