CY62157EV30LL-45ZXI Cypress Semiconductor Corp, CY62157EV30LL-45ZXI Datasheet - Page 7

• Manufacturer Part Number: CY62157EV30LL-45ZXI
• Description: IC SRAM 8MBIT 45NS 48TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62157EV30LL-45ZXI

• Memory Size: 8M (512K x 16)
• Package / Case: 48-TSOP I
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Density: 8Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: TSOP-I
• Operating Temp Range: -40C to 85C
• Supply Current: 25mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 16b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2080-5; CY62157EV30LL-45ZXI

Switching Characteristics
Over the Operating Range
Notes
Document #: 38-05445 Rev. *I
Parameter
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note
18. At any temperature and voltage condition, t
19. t
20. If both byte enables are toggled together, this value is 10 ns.
21. The internal write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
of 0 to V
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
HZOE
, t
HZCE
CC(typ)
[16, 17]
[21]
, t
HZBE
, and output loading of the specified I
, and t
Read cycle time
Address to data valid
Data hold from address change
CE
OE LOW to data valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to High Z
Write cycle time
CE
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
1
1
1
1
1
1
HZWE
LOW and CE
LOW and CE
HIGH and CE
LOW and CE
HIGH and CE
LOW and CE
transitions are measured when the outputs enter a high-impedance state.
HZCE
2
2
2
2
[18]
2
2
[18, 19]
[18]
[18, 19]
HIGH to data valid
HIGH to Low Z
HIGH to power up
HIGH to write end
LOW to High Z
LOW to power down
Description
is less than t
OL
[18, 20]
[18, 19]
/I
OH
as shown in the
LZCE
[18]
[18, 19]
, t
HZBE
is less than t
Figure 4 on page
IL
, BHE, BLE or both = V
LZBE
, t
HZOE
5.
45 ns (Industrial/
Min
45
10
10
45
35
35
35
35
25
10
is less than t
–
–
–
5
–
–
0
–
–
5
–
0
0
0
–
Auto-A)
IL
, and CE
LZOE
2
Max
= V
45
45
22
18
18
45
45
18
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
, and t
IH
CY62157EV30 MoBL
. All signals must be active to initiate a write
HZWE
is less than t
AN13842
Min
55 ns (Auto-E)
55
10
10
10
55
40
40
40
40
25
10
–
–
–
5
–
–
0
–
–
–
0
0
0
–
CC(typ)
for further clarification.
LZWE
/2, input pulse levels
Max
for any device.
55
55
25
20
20
55
55
20
20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 7 of 21
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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