CY62148ELL-55SXIT Cypress Semiconductor Corp, CY62148ELL-55SXIT Datasheet - Page 7
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CY62148ELL-55SXIT
Manufacturer Part Number
CY62148ELL-55SXIT
Description
IC SRAM 4MBIT 55NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Specifications of CY62148ELL-55SXIT
Memory Size
4M (512K x 8)
Format - Memory
RAM
Memory Type
SRAM
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SOIC (11.30mm Width)
Memory Configuration
512K X 8
Access Time
55ns
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Density
4Mb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
19b
Package Type
SOIC
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
20mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
512K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62148ELL-55SXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Waveforms
Notes
Document #: 38-05442 Rev. *H
19. Device is continuously selected. OE, CE = V
20. WE is HIGH for read cycles.
21. Address valid before or similar to CE transition LOW.
22. Data I/O is high impedance if OE = V
23. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
24. During this period, the I/Os are in output state and input signals must not be applied.
DATA OUT
CURRENT
ADDRESS
DATA OUT
ADDRESS
ADDRESS
SUPPLY
DATA I/O
V
CE
OE
CC
WE
OE
CE
NOTE 24
PREVIOUS DATA VALID
HIGH IMPEDANCE
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
t
PU
IH
Figure 4. Read Cycle No. 1 (Address Transition Controlled)
t
LZCE
t
.
SA
t
HZOE
t
t
IL
ACE
LZOE
.
Figure 5. Read Cycle No. 2 (OE Controlled)
t
OHA
50%
t
DOE
t
AA
t
AW
t
t
SCE
RC
t
WC
t
RC
RC
t
t
PWE
DATA VALID
SD
DATA VALID
[20, 21]
[19, 20]
DATA VALID
t
t
HZOE
HA
t
HD
[22, 23]
t
HZCE
CY62148E MoBL
t
PD
50%
IMPEDANCE
HIGH
Page 7 of 14
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