W25Q32BVZPIG Winbond Electronics, W25Q32BVZPIG Datasheet - Page 31

• Manufacturer Part Number: W25Q32BVZPIG
• Description: IC SPI FLASH 32MBIT 8WSON
• Manufacturer: Winbond Electronics

Specifications of W25Q32BVZPIG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Speed: 104MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WSON
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.14 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO
the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 13a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 13b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (See 7.2.20 for detail descriptions).
(IO
(IO
(IO
(IO
CLK
CLK
/CS
/CS
DO
DO
DI
DI
0
1
0
1
)
)
)
)
0
Mode 3
Mode 0
and IO
0
1
23
*
= MSB
*
6
7
24
Figure 13a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 ≠ 10)
1
4
5
. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
25
Byte 1
0
IOs switch from
Input to Output
2
3
26
1
0
1
27
Instruction (BBh)
2
*
6
7
28
3
4
5
29
Byte 2
4
2
3
30
5
0
1
31
6
*
6
7
32
7
4
5
22
23
33
*
Byte 3
8
2
3
A23-16
20
21
34
- 31 -
9
0
1
18
19
35
10
*
6
7
16
17
36
11
4
5
14
15
37
Byte 4
12
2
3
12
13
38
A15-8
13
0
1
10
11
39
Publication Release Date: April 01, 2011
14
6
7
8
9
15
6
7
16
4
5
17
A7-0
2
3
18
W25Q32BV
0
1
19
*
6
7
20
4
5
M7-0
21
Revision F
2
3
22
0
1
23