M25P10-AVMN6P NUMONYX, M25P10-AVMN6P Datasheet - Page 50

• Manufacturer Part Number: M25P10-AVMN6P
• Description: IC FLASH 1MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P10-AVMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 128K X 8bit
• Access Time: 1.4ms
• Memory Ic Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To + 85°C
• Case Style: SOIC
• Base Number: 25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3591; 497-3591

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Table 25.
23-Aug-2007
10-Dec-2007
15-Dec-2008
05-Jun-2006
18-Oct-2007
06-Jul-2007
Date
Document revision history (continued)
Revision
10
11
12
7
8
9
t
the “X” process technology in
SO8 narrow package specifications updated (see
Table
Changed the minimum value for supply voltage.
Added T
maximum
Updated
memory devices on the SPI
Note 1 to
Note 2 below
Changed test condition for I
Removed “low voltage” from the title. Small text changes.
Typical values for Sector Erase and Bulk Erase modified.
UFDFPN8 package (MLP8) added.
Added the reference to a new process technology (code “Y”).
Added notes below
characteristics (device grade
grade
/Y process added to
Code of the UFDFPN8 package modified.
Small text changes.
Applied Numonyx branding.
Added the following to Operating Voltage section of
information
– V = Vcc = 2.7 to 3.6 V for /X parts
– V = Vcc = 2.3 to 3.6 V for /Y parts
RES1
and t
21).
3).
LEAD
Section 3: SPI modes
Table 13: Capacitance
ratings.
RES2
scheme:
and changed maximum value for V
Table 16: Instruction times (device grade 6)
parameter timings changed for devices produced with
Table 10: Operating
Table 24: Ordering information
CC3
bus.
3), and
Table 18
and modified
Changes
in
changed.
Table 14
Table 17: Instruction times (device
and
conditions,
Table
and f
Figure 3: Bus master and
R
IO
19.
Figure 26
in
in
Table 15: DC
scheme.
Table 24.: Ordering
Table
Table 9: Absolute
added.
20.
and