IS61LF51236A-6.5B2I ISSI, Integrated Silicon Solution Inc, IS61LF51236A-6.5B2I Datasheet - Page 24
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS61LF51236A-6.5B2I
Manufacturer Part Number
IS61LF51236A-6.5B2I
Description
IC SRAM 18MBIT 6.5NS 119BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS61LF51236A-7.5TQLI-TR.pdf
(35 pages)
Specifications of IS61LF51236A-6.5B2I
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
6.5ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
119-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61LF51236A-6.5B2I
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS61LF51236A-6.5B2I-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61LF25672A
IS61VF25672A
INSTRUCTION CODES
TAP CONTROLLER STATE DIAGRAM
24
Code
000
001
010
011
100
101
110
111
SAMPLE/PRELOAD
RESERVED
RESERVED
RESERVED
Instruction
SAMPLE-Z
BYPASS
EXTEST
IDCODE
1
0
Test Logic Reset
IS61LF51236A
IS61VF51236A IS61VF102418A
Run Test/Idle
0
Loads the ID register with the vendor ID code and places the register between TDI
Description
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
1
1
0
1
IS61LF102418A
Capture DR
Update DR
Pause DR
Select DR
Exit1 DR
Exit2 DR
Shift DR
0
1
1
1
0
0
0
0
0
1
1
1
0
1
Capture IR
Update IR
Select IR
Pause IR
Exit1 IR
Exit2 IR
Shift IR
0
Integrated Silicon Solution, Inc.
1
1
0
1
0
0
0
0
1
1
07/29/2010
Rev. K