IS42S16320B-7TL ISSI, Integrated Silicon Solution Inc, IS42S16320B-7TL Datasheet - Page 2

• Manufacturer Part Number: IS42S16320B-7TL
• Description: IC SDRAM 512MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16320B-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

of the x8's 134,217,728-bit banks is organized as 8,192
rows by 2048 columns by 8 bits.
The 512Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 512Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
IS42S86400B, IS42/45S16320B
DEVICE OVERVIEW
The 512Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
and 3.3V V
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 134,217,728-bit bank is or-
ganized as 8,192 rows by 1024 columns by 16 bits. Each
2
FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4 BANKS SHOWN)
CKE
RAS
CAS
A10
A12
CLK
BA0
BA1
A11
WE
CS
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ddq
memory systems containing 536,870,912
GENERATOR
COMMAND
DECODER
13
CLOCK
&
ADDRESS
LATCH
ROW
10
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
REGISTER
MODE
COLUMN
COLUMN
13
13
CONTROLLER
COUNTER
REFRESH
REFRESH
CONTROLLER
REFRESH
ADDRESS
BUFFER
dd
SELF
ROW
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A12 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
Integrated Silicon Solution, Inc. — www.issi.com
BANK CONTROL LOGIC
13
8192
16
16
8192
8192
8192
DATA OUT
10
BUFFER
BUFFER
DATA IN
(x 16)
1024
COLUMN DECODER
SENSE AMP I/O GATE
MEMORY CELL
BANK 0
16
16
ARRAY
2
DQML
DQMH
DQ 0-15
V
V
DD
ss
/V
/V
ss
DDQ
Q
04/08/2011
Rev. G