MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet - Page 9
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MT41J64M16LA-187E:B TR
Manufacturer Part Number
MT41J64M16LA-187E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-187E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
533MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
265mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1378-2
Figure 51: MRS to MRS Command Timing (
Figure 52: MRS to nonMRS Command Timing (
Figure 53: Mode Register 0 (MR0) Definitions ................................................................................................ 132
Figure 54: READ Latency .............................................................................................................................. 134
Figure 55: Mode Register 1 (MR1) Definition ................................................................................................. 135
Figure 56: READ Latency (AL = 5, CL = 6) ....................................................................................................... 138
Figure 57: Mode Register 2 (MR2) Definition ................................................................................................. 139
Figure 58: CAS Write Latency ........................................................................................................................ 139
Figure 59: Mode Register 3 (MR3) Definition ................................................................................................. 141
Figure 60: Multipurpose Register (MPR) Block Diagram ................................................................................. 142
Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 145
Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout ......................... 146
Figure 63: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble ................................... 147
Figure 64: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble ................................... 148
Figure 65: ZQ Calibration Timing (ZQCL and ZQCS) ...................................................................................... 150
Figure 66: Example: Meeting
Figure 67: Example:
Figure 68: READ Latency .............................................................................................................................. 153
Figure 69: Consecutive READ Bursts (BL8) .................................................................................................... 155
Figure 70: Consecutive READ Bursts (BC4) .................................................................................................... 155
Figure 71: Nonconsecutive READ Bursts ....................................................................................................... 156
Figure 72: READ (BL8) to WRITE (BL8) .......................................................................................................... 156
Figure 73: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 157
Figure 74: READ to PRECHARGE (BL8) ......................................................................................................... 157
Figure 75: READ to PRECHARGE (BC4) ......................................................................................................... 158
Figure 76: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 158
Figure 77: READ with Auto Precharge (AL = 4, CL = 6) .................................................................................... 158
Figure 78: Data Output Timing –
Figure 79: Data Strobe Timing – READs ......................................................................................................... 161
Figure 80: Method for Calculating
Figure 81:
Figure 82:
Figure 83:
Figure 84:
Figure 85: WRITE Burst ................................................................................................................................ 166
Figure 86: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 167
Figure 87: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF ............................................................ 167
Figure 88: Nonconsecutive WRITE to WRITE ................................................................................................. 168
Figure 89: WRITE (BL8) to READ (BL8) .......................................................................................................... 168
Figure 90: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 169
Figure 91: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 170
Figure 92: WRITE (BL8) to PRECHARGE ........................................................................................................ 171
Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 171
Figure 94: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 172
Figure 95: Data Input Timing ........................................................................................................................ 173
Figure 96: Self Refresh Entry/Exit Timing ...................................................................................................... 175
Figure 97: Active Power-Down Entry and Exit ................................................................................................ 179
Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................ 180
Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ............................................................... 180
Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP) .......................................... 181
Figure 101: Power-Down Entry After WRITE .................................................................................................. 181
Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 182
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
t
t
t
t
RPRE Timing ............................................................................................................................... 162
RPST Timing ............................................................................................................................... 163
WPRE Timing .............................................................................................................................. 165
WPST Timing .............................................................................................................................. 165
t
FAW ............................................................................................................................. 152
t
RRD (MIN) and
t
DQSQ and Data Valid Window ................................................................... 160
t
LZ and
t
HZ .............................................................................................. 162
t
MRD) ......................................................................................... 130
t
RCD (MIN) ............................................................................. 151
t
MOD) .................................................................................. 131
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1Gb: x4, x8, x16 DDR3 SDRAM
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