MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet - Page 188
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-187E:B TR
Manufacturer Part Number
MT41J64M16LA-187E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-187E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
533MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
265mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1378-2
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Table 80: Truth Table – ODT (Nominal)
Note 1 applies to the entire table
Table 81: ODT Parameter
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
ODTL off
ODTL on
Symbol
t
t
ODTH4
ODTH8
AONPD
AOFPD
t
t
AON
AOF
MR1[9, 6, 2]
110 and 111
000–101
000–101
000
000
ODT minimum HIGH time after ODT
ODT turn-off relative to ODTL off
ODT asynchronous turn off delay
ODT turn-on relative to ODTL on
ODT asynchronous turn on delay
ODT synchronous turn off delay
ODT synchronous turn on delay
ODT minimum HIGH time after
assertion or write (BC4)
Notes:
ODT Pin
Description
completion
completion
write (BL8)
0
1
0
1
X
Nominal ODT resistance R
(MR1) Definition. The R
mentioned. DDR3 SDRAM supports multiple R
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. R
the DRAM is initialized, calibrated, and not performing read access or when it is not in
self refresh mode.
Write accesses use R
ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 83 (page 190)). ODT
timings are summarized in Table 81 (page 188), as well as listed in Table 54 (page 76).
Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 194).
1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 189) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal
3. ODT must be disabled during reads. The R
to have it off during writes.
ic ODT is applicable if enabled.
R
TT,nom
DRAM Termination State
R
R
R
R
TT,nom
TT,nom
TT,nom
TT,nom
reserved, ODT on or off
disabled, ODT off
TT,nom
enabled, ODT off
disabled, ODT on
enabled, ODT on
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
Completion of ODTL
Completion of ODTL
or write registration
Write registration
with ODT HIGH
with ODT HIGH
TT,nom
Begins at
TT,nom
if dynamic ODT (R
188
off
on
termination value applies to the output pins previously
is defined by MR1[9, 6, 2], as shown in Mode Register 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT,nom
ODT registered
ODT registered
R
R
Defined to
TT,nom
TT,on
TT,off
TT(WR)
Any valid except self refresh, read
Any valid except self refresh, read
1Gb: x4, x8, x16 DDR3 SDRAM
TT,nom
R
R
R
R
LOW
LOW
termination is allowed any time after
TT,off
TT,off
TT,on
TT,on
±
±
value is restricted during writes. Dynam-
t
t
AON
) is disabled. If R
AOF
On-Die Termination (ODT)
values based on RZQ/n where n
DRAM State
Any valid
Any valid
See Table 54 (page 76)
Illegal
Definition for All
DDR3 Speed Bins
© 2006 Micron Technology, Inc. All rights reserved.
0.5
CWL + AL - 2
CWL + AL - 2
t
CK ± 0.2
2–8.5
2–8.5
4
6
TT,nom
t
t
CK
CK
t
CK
is used dur-
Notes
Units
t
t
t
t
t
CK
CK
ns
ns
CK
CK
ps
CK
2
3
2
3
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