IS42S32400B-7BI ISSI, Integrated Silicon Solution Inc, IS42S32400B-7BI Datasheet - Page 19

• Manufacturer Part Number: IS42S32400B-7BI
• Description: IC SDRAM 128MBIT 143MHZ 90FBGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S32400B-7BI

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS42S32400B
FUNCTIONAL DESCRIPTION
The 128Mb SDRAMs are quad-bank DRAMs which operate
at 3.3V and include a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK).
Each of the 33,554,432-bit banks is organized as 4,096
rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-A11 select the row).
The address bits A0-A7 registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00J
03/03/09
1-800-379-4774
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 128M SDRAM is initialized after the power is applied to
V
DQM High and CKE High.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 100µs period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100µs delay has been satisfied. All banks
must be precharged. This will leave all banks in an idle state
after which at least two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is then ready for mode register programming.
The mode register should be loaded prior to applying any
operational command because it will power up in an un-
known state.
DD
and V
DDQ
(simultaneously) and the clock is stable with
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