IS61LV12816L-10LQI ISSI, Integrated Silicon Solution Inc, IS61LV12816L-10LQI Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS61LV12816L-10LQI
Manufacturer Part Number
IS61LV12816L-10LQI
Description
IC SRAM 2MBIT 10NS 44LQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS61LV12816L-10TL.pdf
(16 pages)
Specifications of IS61LV12816L-10LQI
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
2M (128K x 16)
Speed
10ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61LV12816L-10LQI
Manufacturer:
ISSI
Quantity:
647
Company:
Part Number:
IS61LV12816L-10LQI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS61LV12816L-10LQI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61LV12816L
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. F
10/27/05
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t
referenced to the rising or falling edge of the signal that terminates the Write.
ADDRESS
UB, LB
D
OUT
WE
D
OE
CE
IN
LOW
DATA UNDEFINED
(LB, UB Controlled, Back-to-Back Write)
t
HZWE
ADDRESS 1
t
SD
t
t
WORD 1
SA
WC
t
PBW
HIGH-Z
DATA
VALID
IN
1-800-379-4774
t
t
HD
HA
t
SA
ADDRESS 2
t
t
(1,3)
SD
WC
WORD 2
t
PBW
DATA
VALID
IN
t
LZWE
SA
t
HD
t
, t
HA
HA
, t
SD
, and t
UB_CEWR4.eps
HD
ISSI
timing is
11
®