IS42S16400D-7TLI ISSI, Integrated Silicon Solution Inc, IS42S16400D-7TLI Datasheet - Page 20

• Manufacturer Part Number: IS42S16400D-7TLI
• Description: IC SDRAM 64MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400D-7TLI

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 110mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S16400D
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to
a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a READ
or WRITE command may be issued to that row, subject to
the t
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a t
125 MHz clock (8ns period) results in 2.5 clocks, rounded
to 3. This is reflected in the following example, which
covers any case where 2 < [t
same procedure is used to convert other specification
limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by t
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by t
20
Example: Meeting t
RCD
specification. Minimum t
COMMAND
RCD
RCD
RC
.
specification of 20ns with a
CLK
(MIN) when 2
RCD
RCD
(MIN)/t
should be divided by
ACTIVE
RRD
T0
CK
.
]
3. (The
[t
t
NOP
RCD
RCD
T1
(min)/t
Activating Specific Row Within Specific Bank
BA0, BA1
A0-A11
NOP
CK
Integrated Silicon Solution, Inc. — www.issi.com
T2
CKE
RAS
CAS
CLK
WE
]
CS
3
HIGH - Z
READ or
WRITE
T3
DON'T CARE
BANK ADDRESS
ROW ADDRESS
T4
11/21/07
Rev. E