AC530 Fastrax, AC530 Datasheet - Page 12

• Manufacturer Part Number: AC530
• Description: GPS Development Tools Application Board for UC530
• Manufacturer: Fastrax

Specifications of AC530

• Rohs: yes
• Product: Application Boards
• Tool Is For Evaluation Of: UC530
• Frequency: 1.575 GHz
• Operating Supply Voltage: 3.3 V
• Interface Type: UART
• Description/function: Fastrax Application Board AC530 provides the UC530 connectivity to the Fastrax Evaluation Kit or to other evaluation purposes
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 25 mA

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After waking up the receiver will use all internal aiding like GPS time, Ephemeris, Last Position etc. resulting to a
fastest possible TTFF in either Hot or Warm start Modes.
3.9
Backup State
Backup State means a low quiescent (5 µA typ. at VDD_B) power state where receiver operation is stopped; only
the backup supply VDD_B is powered on while the main supply VDD is switched off by host or by UC530, see also
chapter 3.3. Waking up from Backup State to Full Power is controlled by host by switching on the VDD supply.
In optional Autonomous Backup Mode the UC530 module controls the VDD switching autonomously via the TIMER
signal, see reference circuit in chapter 7.1 by sending NMEA command $PMTK225,4, see chapter 3.3. The
Autonomous Backup Mode is thus similar to Backup State but with autonomous control of external VDD power
switch.
Note that when using an external VDD power switch in low power modes the host needs to enable GPS operation
after initial power up by controlling GPS_ON signal (see reference circuit in chapter 7.1) to high state. The module
can control the VDD power switch autonomously via TIMER signal only after the UC530 is set to Periodic, Backup
or to AlwaysLocate™ mode by a NMEA command.
After waking up the receiver will use all internal aiding like GPS time, Ephemeris, Last Position etc. resulting to a
fastest possible TTFF in either Hot or Warm start modes.
During Autonomous Backup Mode or Backup State the I/O block is powered off; thus suggestion is that host shall
force it’s outputs to low state or to high-Z state during Backup state to minimize small leakage currents (<10 µA
typ.) at receiver’s input signals.
3.10 Reset State
Reset State stops all internal operations and it is entered internally at power up after which internal reset state is
relaxed when 167 ms (typ.) has elapsed and module operations begin. The power on reset level is 2.7 +/- 0.1 V at
VDD. Host can also override Reset State via RESET_N input, which is low state active. Normally external reset
override is not required and RESET_N signal can be left floating (not connected).
2012-05-03
UC530_Datasheet