IS42S16100E-6TL-TR ISSI, Integrated Silicon Solution Inc, IS42S16100E-6TL-TR Datasheet - Page 33

• Manufacturer Part Number: IS42S16100E-6TL-TR
• Description: IC SDRAM 16MBIT 166MHZ 50TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16100E-6TL-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 16M (1M x 16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 50-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S16100E, IC42S16100E
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100E/IC42S16100E can output data
continuously from the burst start address (a) to location
a+255 during a read cycle in which the burst length is set
to full page. The IS42S16100E/IC42S16100E repeats the
operation starting at the 256th cycle with the data output
returning to location (a) and continuing with a+1, a+2, a+3,
etc. A burst stop command must be executed to terminate
this cycle. A precharge command must be executed within
the ACT to PRE command period (t
burst stop command.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
READ A0
READ A0
ras
max.) following the
D
OUT
A0 D
D
OUT
OUT
A0
A0 D
After the period (t
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (t
CAS latency is two and three clock cycle when the CAS
latency is three.
D
OUT
OUT
CAS Latency
A1
A0
BURST STOP
BURST STOP
t
rbd
D
D
OUT
OUT
BST
BST
A2
A1
rbd
rbd
) required for burst data output to
t
RBD
D
D
) is two clock cycle when the
OUT
OUT
t
RBD
A3
A2
3
3
D
OUT
HI-Z
A3
HI-Z
2
2
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