SI1557DH-T1 Vishay/Siliconix, SI1557DH-T1 Datasheet - Page 11

• Manufacturer Part Number: SI1557DH-T1
• Description: MOSFET N/P-Ch 12V 1.0/0.56A
• Manufacturer: Vishay/Siliconix

Specifications of SI1557DH-T1

• Product Category: MOSFET
• Transistor Polarity: N and P-Channel
• Drain-source Breakdown Voltage: +/- 12 V
• Gate-source Breakdown Voltage: +/- 8 V
• Continuous Drain Current: 1.3 A, 0.86 A
• Resistance Drain-source Rds (on): 0.235 Ohms at 4.5 V, 0.535 Ohms at - 4.5 V
• Configuration: Dual
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-363-6
• Fall Time: 10 nS, 10 nS
• Forward Transconductance Gfs (max / Min): 0.8 S, 1.2 S
• Gate Charge Qg: 0.8 nC, 1.1 nC
• Minimum Operating Temperature: - 55 C
• Power Dissipation: 600 mW
• Rise Time: 25 nS, 30 nS
• Factory Pack Quantity: 3000
• Tradename: TrenchFET
• Typical Turn-off Delay Time: 25 nS, 15 nS

AN816
Vishay Siliconix
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the dual SC-70 6-pin package is
measured as junction-to-foot thermal resistance, in which the
“foot” is the drain lead of the device as it connects with the
body. The junction-to-foot thermal resistance for this device is
typically 80_C/W, with a maximum thermal resistance of
approximately 100_C/W. This data compares favorably with
another compact, dual-channel package – the dual TSOP-6 –
which features a typical thermal resistance of 75_C/W and a
maximum of 90_C/W.
Power Dissipation
The typical Rθ
copper leadframe is 224_C/W steady-state, compared to
413_C/W for the Alloy 42 version. All figures are based on the
1-inch
thermal resistance impacts power dissipation for the dual 6-pin
SC-70 package at varying ambient temperatures.
Alloy 42 Leadframe
www.vishay.com
2
ALLOY 42 LEADFRAME
Room Ambient 25 _C
2
P
P
P
FR4 test board. The following example shows how the
D
D
D
+
+ 150
+ 303 mW
T
J(max)
413
JA
Rq
o
S1
G1
D2
C * 25
for the dual-channel 6-pin SC-70 with a
o
JA
* T
C W
SC70−6 DUAL
Front of Board SC70-6
A
o
C
Elevated Ambient 60 _C
P
P
P
D
D
D
+
+ 150
+ 218 mW
D1
G2
S2
T
J(max)
413
Rq
o
C * 60
o
JA
* T
C W
A
o
C
FIGURE 3.
Although they are intended for low-power applications,
devices in the 6-pin SC-70 dual-channel configuration will
handle power dissipation in excess of 0.5 W.
TESTING
To further aid the comparison of copper and Alloy 42
leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin
SC-70 thermal performance on two different board sizes and
pad patterns. The measured steady-state values of Rθ
the dual 6-pin SC-70 with varying leadframes are as follows:
The results indicate that designers can reduce thermal
resistance (θJA) by 34% simply by using the copper leadframe
device as opposed to the Alloy 42 version. In this example, a
174_C/W reduction was achieved without an increase in board
area. If an increase in board size is feasible, a further 120_C/W
reduction can be obtained by utilizing a 1-inch
The Dual copper leadframe versions have the following suffix:
COOPER LEADFRAME
LITTLE FOOT 6-PIN SC-70
1) Minimum recommended pad pattern on
the EVB board (see Figure 3).
2) Industry standard 1-inch
maximum copper both sides.
Room Ambient 25 _C
P
P
P
D
D
D
+
+ 150
+ 558 mW
vishay.com
T
J(max)
Back of Board SC70-6
224
Rq
o
C * 25
Dual:
Compl.:
o
JA
* T
C W
2
PCB with
A
o
C
Elevated Ambient 60 _C
P
P
P
Si19xxEDH
Si15xxEDH
D
D
D
Alloy 42
518_C/W
413_C/W
+
+ 150
+ 402 mW
Document Number: 71405
T
J(max)
224
Rq
o
C * 60
2
o
. PCB area.
JA
* T
C W
Copper
344_C/W
224_C/W
A
12-Dec-03
o
C
JA
for