EVAL-AD5689RSDZ Analog Devices, EVAL-AD5689RSDZ Datasheet

EVAL-AD5689RSDZ

Manufacturer Part Number

EVAL-AD5689RSDZ

Description

Data Conversion IC Development Tools EVALUATION BOARD

Manufacturer

Analog Devices

Type

DACr

Datasheet

1.EVAL-AD5687RSDZ.pdf (28 pages)

Specifications of EVAL-AD5689RSDZ

Rohs

yes

Product

Evaluation Boards

Tool Is For Evaluation Of

AD5689R

Operating Supply Voltage

2.7 V to 5.5 V

Factory Pack Quantity

Current page: 1 of 28
Download datasheet (675Kb)

Data Sheet

FEATURES

High relative accuracy (INL):

Low drift 2.5 V reference: 2 ppm/°C typical

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

TUE: ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User-selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

50 MHz SPI with readback or daisy chain

Low glitch: 0.5 nV-sec

Robust 4 kV HBM and 1.5 kV FICDM ESD ratings

Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Optical transceivers

Base station power amplifiers

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

GENERAL DESCRIPTION

The

family are low power, dual, 16-/12-bit buffered voltage output

digital-to-analog converters (DACs). The devices include

a 2.5 V, 2 ppm/°C internal reference (enabled by default)

and a gain select pin giving a full-scale output of 2.5 V

(gain = 1) or 5 V (gain = 2). The devices operate from

a single 2.7 V to 5.5 V supply, are guaranteed monotonic

by design, and exhibit less than 0.1% FSR gain error and

1.5 mV offset error performance. Both devices are available

in a 3 mm × 3 mm LFCSP and a TSSOP package.

The

circuit and a RSTSEL pin that ensure that the DAC outputs

power up to zero scale or midscale and remain there until

a valid write takes place. Each part contains a per channel

power-down feature that reduces the current consumption

of the device to 4 µA at 3 V while in power-down mode.

The

interface (SPI) that operates at clock rates up to 50 MHz.

and both devices contain a V

1.8 V/3 V/5 V logic.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

AD5689R/AD5687R

members of the nanoDAC+™

also incorporate a power-on reset

use a versatile serial peripheral

LOGIC

±2 LSB maximum at 16 bits

pin that is intended for

Document Feedback

with 2 ppm/°C Reference, SPI Interface

Table 1. Dual nanoDAC+ Devices

Interface

SPI

PRODUCT HIGHLIGHTS

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

High Relative Accuracy (INL).

Low Drift 2.5 V On-Chip Reference.

Two Package Options.

SCLK

SYNC

LOGIC

SDIN

SDO

AD5689R

AD5687R

2 ppm/°C typical temperature coefficient

5 ppm/°C maximum temperature coefficient

3 mm × 3 mm, 16-lead LFCSP

16-lead TSSOP

Dual, 16-/12-Bit nanoDAC+

Reference

Internal

External

Internal

External

AD5689R/AD5687R

LDAC RESET

FUNCTIONAL BLOCK DIAGRAM

(16-bit): ±2 LSB maximum

(12-bit): ±1 LSB maximum

INPUT

AD5689R/AD5687R

POWER-ON

GND

16-Bit

AD5689R

AD5689

N/A

RSTSEL

RESET

Figure 1.

DAC

STRING

DAC A

DAC B

GAIN =

×1/×2

GAIN

REF

12-Bit

AD5687R

AD5687

AD5697R

N/A

REFERENCE

BUFFER

2.5V

www.analog.com

POWER-

DOWN

LOGIC

OUT

Related parts for EVAL-AD5689RSDZ

EVAL-AD5689RSDZ Summary of contents

Page 1

... Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...

Page 2

AD5689R/AD5687R TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Characteristics ........................................................................ 5 Timing Characteristics ................................................................ 6 Daisy-Chain and ...

Page 3

Data Sheet SPECIFICATIONS 5.5 V; 1.8 V ≤ V ≤ 5.5 V; all specifications T DD LOGIC Table 2. Parameter Min STATIC PERFORMANCE 2 AD5689R Resolution 16 Relative Accuracy Differential Nonlinearity AD5687R Resolution 12 Relative ...

Page 4

AD5689R/AD5687R Parameter Min REFERENCE OUTPUT Output Voltage 7 2.4975 Reference Temperature Coefficient 8, 9 Output Impedance 3 Output Voltage Noise 3 Output Voltage Noise Density 3 Load Regulation Sourcing 3 Load Regulation Sinking 3 Output Current Load Capability 3 Line ...

Page 5

Data Sheet AC CHARACTERISTICS kΩ to GND noted. Guaranteed by design and characterization; not production tested. Table 3. Parameter 1 Output Voltage Settling Time AD5689R AD5687R Slew ...

Page 6

AD5689R/AD5687R TIMING CHARACTERISTICS All input signals are specified with 2 5.5 V, 1.8 V ≤ V ≤ 5 LOGIC Table 4. < 2.7 V 1.8 V ≤ V LOGIC ...

Page 7

Data Sheet DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with and Figure 2 5.5 V, 1.8 V ≤ 2 5.5 V. Table 5. 1.8 ...

Page 8

AD5689R/AD5687R SCLK SYNC DB23 SDIN INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23 DB0 DB23 DB0 DB23 UNDEFINED ...

Page 9

Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 6. Parameter V to GND GND LOGIC V to GND OUT V to GND REF Digital Input Voltage to GND Operating Temperature Range Storage ...

Page 10

AD5689R/AD5687R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUT 2 11 GND AD5689R/ AD5687R TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 2. ...

Page 11

Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.5020 DEVICE 1 DEVICE 2 2.5015 DEVICE 3 DEVICE 4 DEVICE 5 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 2.4980 –40 – TEMPERATURE (°C) Figure 8. Internal Reference Voltage vs. Temperature (Grade B) ...

Page 12

AD5689R/AD5687R 2.5000 25°C A 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 –0.005 –0.003 –0.001 0.001 I (A) LOAD Figure 14. Internal Reference Voltage vs. Load Current –2 –4 ...

Page 13

Data Sheet INL 0 DNL –2 –4 – – 25°C A REFERENCE = 2.5V –10 – TEMPERATURE (°C) Figure 20. INL Error and DNL Error vs. Temperature ...

Page 14

AD5689R/AD5687R 1.5 1.0 0.5 0 –0.5 –1 25°C A INTERNAL REFERENCE = 2.5V –1.5 2.7 3.2 3.7 4.2 SUPPLY VOLTAGE (V) Figure 26. Zero-Code Error and Offset Error vs. Supply Voltage 0. ...

Page 15

Data Sheet 1.0 0.8 0.6 0.4 SINKING 2.7V 0.2 0 –0.2 –0.4 –0.6 SOURCING 2.7V –0.8 –1 LOAD CURRENT (mA) Figure 32. Headroom/Footroom vs. Load Current 25° ...

Page 16

AD5689R/AD5687R 25°C A INTERNAL REFERENCE = 2.5V CH1 10µV M1.0s Figure 38. 0 Output Noise Plot, 2.5 V Internal Reference 1600 25°C ...

Page 17

Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical ...

Page 18

AD5689R/AD5687R DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC measured by loading the attack channel with a ...

Page 19

Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS The AD5689R AD5687R are dual 16-/12-bit, serial input, / voltage output DACs with an internal reference. The parts operate from supply voltages of 2 5.5 V. Data is written to the ...

Page 20

AD5689R/AD5687R SERIAL INTERFACE The AD5689R AD5687R have a 3-wire serial interface / ( SYNC , SCLK, and SDIN) that is compatible with SPI, QSPI™, and MICROWIRE® interface standards as well as most DSPs. See Figure 2 for a timing diagram ...

Page 21

AD5689R/AD5687R STANDALONE OPERATION The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 24-bit input shift register on the falling edge of SCLK. After the last of 24 data bits is ...

Page 22

AD5689R/AD5687R READBACK OPERATION Readback mode is invoked through a software executable read- back command. If the SDO output is disabled via the daisy-chain mode disable bit in the control register automatically enabled for the duration of the read ...

Page 23

Data Sheet LOAD DAC (HARDWARE LDAC PIN) The AD5689R/AD5687R DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC ...

Page 24

AD5689R/AD5687R HARDWARE RESET ( RESET ) RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the power-on reset select pin (RSTSEL). RESET ...

Page 25

Data Sheet THERMAL HYSTERESIS Thermal hysteresis is the voltage difference induced on the refer- ence voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. Thermal hysteresis data is shown in Figure 51. It ...

Page 26

... The iCoupler® products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5689R/ AD5687R the number of interface lines is kept to a minimum ...

Page 27

Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE 0.15 0.05 3.10 0.30 3.00 SQ 0.23 2.90 0.18 13 0.50 12 BSC EXPOSED 9 8 0.50 TOP VIEW BOTTOM VIEW 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY ...

Page 28

... AD5689RARUZ-RL7 16 Bits −40°C to +105°C AD5689RBRUZ 16 Bits −40°C to +105°C AD5689RBRUZ-RL7 16 Bits −40°C to +105°C EVAL-AD5689RSDZ AD5687RBCPZ-RL7 12 Bits −40°C to +105°C AD5687RBRUZ 12 Bits −40°C to +105°C AD5687RBRUZ-RL7 12 Bits −40°C to +105°C ...

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