MAX98089EVKIT+TQFN Maxim Integrated, MAX98089EVKIT+TQFN Datasheet - Page 85

• Manufacturer Part Number: MAX98089EVKIT+TQFN
• Description: Audio IC Development Tools
• Manufacturer: Maxim Integrated
• Type: Audio CODECr

Specifications of MAX98089EVKIT+TQFN

• Product: Evaluation Kits
• Tool Is For Evaluation Of: MAX98089
• Operating Supply Voltage: 2.8 V to 5.5 V
• Interface Type: I2C
• Operating Supply Current: 1 A

The digital signal paths in the IC require a master clock
(MCLK) between 10MHz and 60MHz to function. The
MAX98089 requires an internal clock between 10MHz
and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to
create the internal clock (PCLK). PCLK is used to clock
all portions of the IC.
The MAX98089 includes two digital audio signal paths,
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, four main clocking modes are
supported:
U PLL Mode: When operating in slave mode, enable the
Table 11. Clock Control Registers
Maxim Integrated
REGISTER
0x11/0x19
PLL to lock onto any LRCLK input. This mode requires
the least configuration, but provides the lowest per-
formance. Use this mode to simplify initial setup or
when normal mode and exact integer mode cannot
be used.
0x10
BIT
5
4
7
6
5
4
SR1/SR2
PSCLK
NAME
MCLK Prescaler
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz P MCLK P 20MHz (PCLK = MCLK)
10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2)
11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4)
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
Clock Control
Low-Power, Stereo Audio Codec
VALUE
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
with FlexSound Technology
SAMPLE RATE
U Normal Mode: This mode uses a 15-bit clock divider
U Exact Integer Mode (DAI1 only): In both master and
U DAC Low-Power Mode: This mode bypasses the
Reserved
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequen-
cies and can be used in either master or slave mode.
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
PLL for reduce power consumptions and uses fixed
counters to generate the clocks. The DAI__DAC_LP
bits override the other clock settings.
11.025
(kHz)
22.05
44.1
16
24
32
8
DESCRIPTION
VALUE
0xA
0xB
0xC
0xD
0x8
0x9
0xE
0xF
MAX98089
SAMPLE RATE
Reserved
Reserved
Reserved
Reserved
Reserved
(kHz)
88.2
48
96
85