EVAL-AD7656CBZ Analog Devices, EVAL-AD7656CBZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD7656CBZ
• Description: Data Conversion IC Development Tools evaluation control board.
• Manufacturer: Analog Devices
• Type: ADCr

Specifications of EVAL-AD7656CBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD7656
• Interface Type: Parallel, Serial
• Operating Supply Voltage: 12 V
• For Use With: EVAL-CONTROL-BRD2

Data Sheet
TIMING SPECIFICATIONS
AV
T
Table 4.
Parameter
PARALLEL MODE
PARALLEL WRITE OPERATION
PARALLEL READ OPERATION
SERIAL INTERFACE
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with t
A buffer is used on the data output pins for this measurement.
A
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
CC
= T
SCLK
CONVERT
QUIET
ACQ
10
1
WAKE-UP
11
12
13
14
15
2
3
4
5
6
7
8
9
16
17
18
19
20
21
2
/DV
MIN
CC
to T
= 4.75 V to 5.25 V, V
MAX
, unless otherwise noted.
V
3
150
550
25
60
2
25
15
0
5
5
5
0
0
0
45
45
10
12
6
18
12
22
0.4 t
0.4 t
10
18
DRIVE
SCLK
SCLK
< 4.75 V
DD
= 5 V to 16.5 V, V
Limit at T
1
V
3
150
550
25
60
2
25
15
0
5
5
5
0
0
0
36
36
10
12
6
18
12
22
0.4 t
0.4 t
10
18
Figure 2. Load Circuit for Digital Output Timing Specification
DRIVE
MIN,
SCLK
SCLK
= 4.75 V to 5.25 V
T
TO OUTPUT
MAX
SS
= −5 V to −16.5 V, V
PIN
25pF
Rev. D | Page 9 of 32
C
L
200µA
200µA
Unit
µs typ
ns min
ns min
ns min
ns max
ms max
µs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
I
I
OL
OH
DRIVE
R
= t
= 2.7 V to 5.25 V, V
F
Description
Conversion time, internal clock
Minimum quiet time required between bus relinquish
and start of next conversion
Acquisition time
Minimum CONVST low pulse
CONVST high to BUSY high
STBY rising edge to CONVST rising edge
Partial power-down mode
WR pulse width
CS to WR setup time
CS to WR hold time
Data setup time before WR rising edge
Data hold after WR rising edge
BUSY to RD delay
CS to RD setup time
CS to RD hold time
RD pulse width
Data access time after RD falling edge
Data hold time after RD rising edge
Bus relinquish time after RD rising edge
Minimum time between reads
Frequency of serial read clock
Delay from CS until SDATA three-state disabled
Data access time after SCLK rising edge/CS falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time after SCLK falling edge
CS rising edge to SDATA high impedance
1.6V
= 5 ns (10% to 90% of V
AD7656/AD7657/AD7658
REF
DD
) and timed from a voltage level of 1.6 V.
= 2.5 V internal/external,